PIC platform enhancements, developments in design software, and more...
Welcome to issue #4
Welcome to issue #4
Our in-depth coverage of what it takes to deliver practical devices and the innovations allowing photonic integration to reach new heights continues. In December, we put the spotlight on silicon photonics and looked at the challenges and opportunities on the table. Now it’s time to consider platform enhancements being applied by leading labs worldwide that could allow PICs to shine even brighter.
Ségolène Olivier, an R&D project leader on advanced silicon photonics components at Leti, shares some of the latest developments towards more compact, high-performance and power-efficient PICs for telecom networks and data centre applications. And, adding to the picture, Johann Peter Reithmaier from University of Kassel and Gadi Eisenstein from Technion explain what makes the InP quantum dot laser a very promising contender for tomorrow’s optical networks.
Norbert Grote, former deputy director of Fraunhofer HHI’s photonic components department, provides device examples to expand on hybrid integration. And we catch up with Martin Eibelhuber -- a key member of EV Group’s business development team -- to add an industry perspective on what’s helping to advance PIC production.
Also, we continue our focus on chip design and look at opportunities to streamline the development process. André Richter, Sergei Mingaleev and Igor Koltchanov of VPI Photonics discuss the power of a layout-aware schematic-driven design methodology for accelerating the application of integrated photonics.
Plus, we have further updates on Photon Delta’s roadmapping mission, including video-comment from key figures and stakeholders in the PIC community.
Enjoy the issue!
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adding strength to InP photonic integration
The emergence of advanced modulation techniques in optical transmission provided the perfect opportunity for HHI to strengthen work on InP PICs, as Norbert Grote – former deputy director of the organization’s photonic components department and now a senior adviser– explains.
Monolithic photonic integrated circuits (PIC) have been on the agenda at the Berlin, Germany, based Heinrich-Hertz Institute (HHI) since the early 1980s – admittedly a rather ambitious undertaking in those early days of photonics. Some ten years later, PICs could be realized featuring quite a remarkable level of complexity at that time. In particular, a fully integrated heterodyne receiver chip with polarization-diversity architecture was developed comprising 16 optical and electrical elements in total, including balanced waveguide-integrated photodiodes together with field effect transistors for first electrical amplification, a tunable local oscillator BH-DBR type laser, and optical waveguide based couplers, as well as polarization rotator and splitter devices . The emergence of advanced modulation techniques in optical transmission was the perfect opportunity for HHI to strengthen work on InP PICs in the mid of the past decade.
Since then both transmitter and receiver PICs for phase-modulation transmission schemes have been under development, and as a result several designs are now successfully deployed in commercial products or are at the design-in and qualification stage.
On the transmitter side Mach-Zehnder modulator (MZM) based devices have been extensively developed and applied to a range of amplitude/phase modulation formats like OOK, PSK, QPSK, and 16-QAM. The MZM, the core element for providing high-speed, chirp-free, and spectrally broadband (C-band) modulation, features an active capacitively loaded push-pull traveling-wave electrode (TWE) section along with two MMI couplers and spot-size converters for tolerant optical fiber-chip coupling. Each MZM arm integrates a phase electrode to enable adjusting the operation point of the MZ independently of the TWE reverse bias voltage. The switching voltage is in the range of 2 V, and the extinction ratio above 25 dB. Modulation bandwidth up to ~70 GHz has been achieved. Based on this fundamental device, Inverse Quadrature (IQ) modulator PICs consisting of two nested MZMs have been implemented for single and dual-polarization operation. Monitor photodiodes have been incorporated for facilitating setting of the operation points. The integration of both single MZM and IQ MZM with a BH type DFB laser was accomplished as well. A largely extended multichannel PIC design has been implemented recently targeting coherent optical orthogonal frequency division multiplexing (OFDM) and Nyquist wavelength division multiplexing (N-WDM). The complex PIC shown in Fig. 1, an outcome of the European project ASTRON  has an impressive footprint of 15 x 28 mm2 .
Figure 1. Schematic and chip image of an 8-channel InP-based all-optical transmitter PIC for OFDM/Nyquist WDM based transmission systemsCoherent optical orthogonal frequency division multiplexing (OFDM) and Nyquist wavelength division multiplexing (N-WDM) are regarded as promising transmission technologies in future flexible optical networks to generate spectrally efficient superchannels with data rates up to several Tb/s. To this end first monolithic InP-based all-optical 8-channel OFDM transmitter photonic integrated circuits have been developed and fabricated at Fraunhofer HHI in the framework of the EU funded project ASTRON . The presented PIC has been designed for an aggregate data capacity of up to 1Tb/s and integrates 180 optical and electrical functions on a chip area of 15 x 28 mm2. This includes eight travelling-wave-electrode type Mach-Zehnder IQ modulators with integrated 50-Ω thin film termination resistors, a specific 8x8 arrayed waveguide grating (AWG) to achieve optical Fourier transform and signal multiplexing, and a 1x8 optical splitter/combiner as the main building blocks. The electro-optical 3-dB bandwidths of the integrated modulators are in the range of 33 ± 3 GHz .
Different variants of corresponding coherent receiver PICs have been developed and used in conjunction with single and dual-polarization QPSK and QAM modulation formats. Essentially those chips consist of multimode interference (MMI) coupler-based 90° hybrids, high-speed waveguide-integrated photodiodes, and an optical input spot-size converter at the input. In addition, variable optical attenuators in the form of a thermally tunable Mach-Zehnder interferometer have been incorporated in the signal path for providing intensity control . The most recent design has managed a symbol rate of 100 GBaud . This has been rendered possible by using improved photodiode structures featuring an optoelectronic bandwidth of 90 GHz along with a responsivity of around 0.5 A/W at 1550 nm wavelength. Due to the polarization independent design of the 90°-hybrid intra-symbol phase errors of less than + 5 ° have been achieved over the entire C-band. The latter receiver chip measures only 3.5 mm2 in size.
Traditional amplitude modulation is yet the easiest way for data generation. And for this, transmitters relying on electro-absorption modulators (EAM) integrated with DFB laser diodes are particularly attractive because of their ultra-high speed and low-chirp potential. At HHI, electro-absorption modulated lasers (EML) have been developed for quite a few years using a fairly simple design in that both the laser and the modulator share the same layer structure. Electrical isolation of both parts is accomplished by an etched trench. In fact, apart from this step the entire EML fabrication is almost identical to that of an ordinary DFB laser. To date up to 70 Gb/s direct modulation has been demonstrated on such components, and accessibility of 100 Gb/s is foreseeable. A drawback of EMLs compared to DFB lasers is the moderate optical output power. To overcome this limitation the structure was extended recently by additionally integrating an optical amplifier section in the same manner as done with the EAM section. 10 dBm of optical output power has been achieved in this way even at a bit rate of 56 Gb/s. And finally, a 4-channel array consisting of such EML structures has been realized that in total is capable of delivering more than 200 Gb/s from a single chip of an area of just 1.8 mm2 (Fig. 2, ). Such components are regarded as highly attractive for data centres, even if this booming application field is commonly believed to be the realm of Si-photonics.
Figure 2. 4-channel array of 56 Gb/s electro-absorption modulated DFB lasers (EML)Each EML in the array consists of three different integrated elements: DFB laser diode, electro-absorption modulator (EAM), and an optical amplifier (SOA) to boost the output power. All of them rely on the same structure, including an InGaAlAs MQW active region, which not only largely eases fabrication but also ensures low-loss optical coupling and negligible optical reflections between the different sections. To ensure transparency of the modulator in the on-state the DFB wavelength is shifted towards the long-wavelength side of the gain spectrum by design. In the presented array each EML exhibits a different emission wavelength (~1569 – 1577 nm range) with a spacing of 2.5 nm. All devices are electrically accessible from the back side. The 4-EML array measures 2.5 mm x 0.7 mm. Each individual EML is capable of 56 Gb/s modulation enabling generation of a total bit rate of 224 Gb/s from the 4-array component. No noticeable interference on bit-error-rate behavior was found when simultaneously operating adjacent EMLs. Typical peak-peak modulation voltage amounts to 2 Vpp around a bias voltage in the 1.1-1.4 V range . The EML transmitter array can be used in space division multiplexing mode with four separate fibers (PSM4) or for wavelength division multiplexing schemes (WDM).
The PIC implementations outlined above are relying on dedicated designs and technology for optimized performance. For photonic integrated circuits to become more widely deployed in diverse application sectors, the adoption of a foundry business model in photonics is highly convincing. For this goal InP is unique in that it provides the only materials platform allowing for integration of virtually all optical functionalities required, in particular those needed for light generation and amplification which is not feasible in silicon.
The foundry approach was tackled in the recent EU projects EuroPIC  and PARADIGM  which were geared towards investigating and establishing the entire eco-system needed for making generic InP photonic integration a reality. Accordingly, the work program encompassed development of integration technology and building blocks; design platform and tools; process design kits (PDK); and (to a lesser extent) generic PIC packaging. The latter task is now extensively being continued in the recently started EU Pilot Line project PIXAPP . Fraunhofer HHI was and is participating in these projects. In EuroPIC & PARADIGM it was mainly engaged with technological platform development and execution of “foundry” wafer runs implementing PIC designs from project-external users.
Figure 3. Waveguide-based polarization converter integrated between EAMs
A polarization converter rotating the plane of polarization represents a key optical element for managing polarization in a PIC. On HHI’s platform a structure has been adopted that consists of two ridge-waveguide sections with slanted sidewalls. Thanks to a refined design the most critical fabrication tolerance could be significantly relaxed to ~ +/- 10%, compared to previous designs, whilst still allowing for a TE/TM extinction ratio (ER) of 20 dB. Experimental results have so far shown ER levels of 15 dB over the full C-band, and an insertion loss of < 1 dB (TE) . The total device length including transition tapers amounts to some 700 µm. The photograph shows an image of such a polarization converter integrated between two serial electro-optical modulators to enable polarization-multiplexed modulation. 
The starting point of HHI’s generic platform development was the high-speed waveguide-integrated photodiode structure which has been a key component in HHI’s research portfolio since the early 1990’s and which, by the way, served as “starter kit” of u2t Photonics (now Finisar Germany GmbH), when founded as a spin-off company of HHI in 1998. This PD structure, including an evanescently coupled waveguide section, represents the main building block for the receiver (Rx) part of the PIC platform. With three different waveguide designs available to support bending radii down to 150 µm, a variety of passive optical building blocks has been introduced, amongst them polarization splitter and converter [10, 11] (Fig. 3) elements for polarization handling. The full capability of InP based photonic integration is achieved by subjoining transmitter-type (Tx) building blocks: mainly gain elements/optical amplifiers; lasers; phase shifter and modulator devices. A schematic of the entire platform , referred to as TxRx platform, is depicted in Fig. 4, and Table 1 gives an overview on the currently available building blocks. A crucial feature of HHI’s unique platform concept is the use of semi-insulating substrate and waveguide material which favors high-frequency performance and supports electrical isolation and reduction of electrical crosstalk effects.
Figure 4. Schematic layer structure and basic building blocks of HHI’s TxRx PIC platformThe generic PIC fabrication process commences with the growth of the base wafer layers (indicated by the white arrow) consisting of a Fe doped InGaAsP/InP waveguide layer stack and the half-structure of a laser (“Tx structure”), all deposited on a semi-insulating InP:Fe substrate. The active region, designed for C-band operation, is formed of an offset multi-quantum well (MQW) stack on top of a quaternary bulk waveguide layer. This stack is used to create laser gain elements, SOAs and electro-absorption modulators (EAM). At places where DFB laser elements are to be positioned 1st-order complex-coupled DFB gratings are formed. In the same way tunable Bragg gratings (BG), a building block for e. g. wavelength tunable DBR lasers or vertical coupling structures, are implemented after locally etching off the MQW material. Without grating, this section can be used for electro-optical phase shifters (PS). The Tx elements are mesa-etched down to the insulating bottom waveguide region thus providing full electrical isolation. These steps are followed by the selective-area growth of the “optical passives & photodiode” layer stack. The same passive waveguide layer interconnects both the photodiode (evanescent coupling) and the Tx devices (butt-jont coupling) and serves for building all of the passive optical elements. The entire wafer fabrication involves only three epitaxial growth steps, including base wafer growth, and about 25 lithographic mask levels. The individual chips are delivered with facet coating according to customers’ needs.
A distinct advantage of generic platforms is the possibility to execute multi- project wafer (MPW) runs shared by multiple users. HHI has launched MPW runs on a semi-commercial basis in 2014, now scheduling four runs per year. Including the runs performed in previous projects more than 60 different PIC designs from industry and academic groups have been fabricated meanwhile (example shown in Fig. 5). An individual user can choose a minimum design cell of 4x12 mm2, or a multiple thereof, allowing for very affordable prices for prototype chips. PDK implementations are being offered and maintained by a number of established vendors of photonic design & simulation software: PhoeniX BV; Photon Design Ltd.; VPI Photonics GmbH; Filarete S.r.l.; and Lumerical Solutions, Inc. (in progress). MPW runs may be accessed by contacting JePPIX  providing brokerage services or HHI directly, and also through the EU-projects ACTPHAST  and PICs4ALL .
Table 1. Compilation of building blocks (BB) currently offered on HHI’s InP integration platform
JePPIX, the prime consortium of European stakeholders in photonic integration, plays a pivotal role in this community. Besides brokering activities it is, amongst others, involved in promoting PIC technology to broaden awareness in the public and professional domain; in developing and maintaining road maps; and not least in organizing PIC training. Through the latter newcomers and advanced learners are educated in not just PIC design, but also made aware of new market opportunities. Such training sessions have been held in JePPIX’s “hometown” Eindhoven, The Netherlands, for many years, but have recently been stretched out worldwide, with events organized in Boston (US), New York (US)*; Daejeon (S. Korea); and end of 2016 in Santa Clara (US)* and Beijing (P.R.C) (* principal organizer: 7pennies Consulting).
Figure 5. Example of customer specific PIC made on HHI’s MPW platform
To cope with the growing capacity and coverage demand for wireless services the EU-COMANDER project  has proposed a Next Generation Network that merges the optical and wireless infrastructures. A key component thereof is a Remote Access Unit. A respective PIC was designed by Bright Photonics BV and fabricated on a MPW run at HHI. The photonic circuit utilizing arrayed waveguide gratings (AWG) as demultiplexer to provide six discrete spectral passbands between 1510 nm and 1570 nm - is intended for Fiber-To-The-Home (FTTH) and Radio-over-Fiber (RoF) services . Further building blocks used in the design are tuneable DBR and DFB laser diodes, SOAs, current-injection tuneable Bragg gratings, high-speed photodiodes and thermo-optic phase shifters. In full operation all signals are processed simultaneously by dedicated tuneable receiver and transmitter sub-circuits.
Despite the high capabilities of monolithic InP – and likewise Si – based photonic integration platforms ultimate limitations in performance and complexity may not be ignored. Hybridization of PICs implemented on different classes of materials is considered an efficient way to expand those limits. In Si photonics hybrid (or hetero-) integration of InP-based light sources/ amplifiers is inevitable to achieve full TxRx functionalities.
The combination with dielectric material platforms, made e.g. of SiNx or polymers, is another dimension to create integrated optical components with enhanced performance. Optical chip-to-chip connectivity is the big technological challenge here. To this end, various solutions are being currently explored by many groups. HHI has been pursuing a polymer based hybrid integration platform  for many years but is also engaged in other hybrid developments by contributing adapted active InP devices.. In a recent collaboration with IBM-Watson Research Center, HHI has developed InP optical amplifier arrays that were designed for flip-chip mounting into a Si based waveguide network for optical switching (Fig. 6, ). A specific requirement was to achieve not only optimal coupling performance but also to make the chip fit in-between the waveguides with high longitudinal precision. The latter was accomplished by adopting etched rather than cleaved facets.
Figure 6. Integrated SOA array for hybrid integration onto Si photonics platform
For photonic switch matrices InP based 4-channel SOA arrays have been developed which were flip-chip mounted onto a Si photonic carrier with SiN waveguides. The SOAs with a 250 µm pitch feature tapered spot-size converters at either end for efficient optical coupling to the SiN waveguides and incorporate appropriate flip-chip assembly structures, including reference stops. The facets, tilted by 7 deg, are formed by dry etching to provide lithographic precision of the length (1 mm) of the SOA devices. Fiber coupling to assembled modules demonstrated >10 dB fiber-to-fiber gain over 60 nm bandwidth centered at 1550 nm for all SOA channels. Each SOA was shown to support error-free 4-wavelength 25 Gb/s WDM links (collaboration IBM/HHI )
Norbert Grote joined the Heinrich Hertz Institute in 1981 and was deputy director of the Photonic Components department from 2005 to 2015. Amongst others, he was engaged with laser and PIC related projects as well as hybrid integration technologies based on polymer materials. Today he works for HHI on a freelance basis, particularly in the framework of EU funded PIC projects.
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Production solution: interior view of an automated wafer bonding system
Martin Eibelhuber, a key member of EV Group’s business development team, considers current and future demand for optical chips and looks at production developments shaping future devices. Interview by James Tyrrell.
How did your organization become involved with the development of integrated optical devices?
Over many years, EV Group (EVG) has established itself as a strong partner for universities and research organizations involved in microelectronics and nanoelectronics. These work programs allowed us to learn early on about the key challenges present in photonic integration. Our plasma activated direct wafer bonding technology, which featured in several projects for integrating compound semiconductors on silicon, was soon recognized as a viable way to produce photonic circuits with an on-chip laser source on an industrial scale. Additionally, our nanoimprint lithography (NIL) solutions have triggered a great deal of interest from the photonics community. NIL provides several key advantages such as direct patterning of polymer optical elements and patterning 3D structures, which are of particular interest in the field of photonics.
Your role at EVG brings you into contact with a wide range of customers. How have you seen applications for optical chips evolve, and what uses have particularly captured your imagination?
Mainstream applications today are based on silicon photonics for telecommunication and high-performance computing. The enormous growth of data transmission—particularly from cloud computing and mobile Internet usage—is triggering significant market demand from data centers, and the discussions we have with partners and customers reflect this. Eventually, demand will move even closer to consumer markets and it will be interesting to see which products will adopt silicon photonics first. There is also a lot of fascinating work ongoing to utilize photonic integrated circuits for innovative biosensing devices, and we expect to see more and more activity in this area.
Looking at the production process, what do you see as some of breakthroughs in the realization of today's optical chips?
The ability to manufacture chip-level optical elements like waveguides, modulators and detectors with standard CMOS technologies paved the way for today’s industry. Nonetheless, as silicon is a poor light emitter, the integration of the laser source has always been a main challenge. Thus, the ability to achieve III/V-on-Si hybrid lasers using direct wafer bonding technology has enabled optimal integration schemes. In combination with a wafer-level die transfer process, plasma activated direct wafer bonding has proven to fulfill the needs for volume manufacturing of optical chips.
Considering the future, what are the prospects for pushing device performance to new levels and what challenges stand in the way?
Heterogeneous integration of photonic and electronic chips will realize highly advanced electro-optical microsystems. 3D integration has already shown significant progress in the electronics industry, and wafer-level stacking utilizing through silicon vias (TSVs) is already in volume production. There will be different requirements for the integration of photonic chips. We are confident that wafer bonding will enable the industry to overcome these challenges and manufacture sophisticated electronic/photonic products.
More information – http://www.evgroup.com
Very high data rates and tremendous temperature stability make the InP quantum dot laser a very promising contender for tomorrow’s optical networks. Johann Peter Reithmaier from University of Kassel and Gadi Eisenstein from Technion report on recent progress in the lab and share their results with PIC International’s sister title - Compound Semiconductor magazine.
The semiconductor laser is netting annual sales of billions of dollars, thanks to its deployment in an ever growing number of applications that include optical communication, material processing, medical applications and sensing technologies.
Since the 1980s, sitting at the very heart of this device has been the quantum well. This replaced the bulk material employed beforehand, delivering hikes in reliability and performance. Improvements resulted from the utilisation of a degree of quantum size effects to tailor carrier confinement and tune emission wavelength.
One should not think, however, that the quantum well active region is ideal. It suffers from severe intrinsic problems, and is a far from perfect gain material. Flaws include a laser performance that is strongly dependent on the device’s operation temperature, due to the occupation of carriers in states that fail to contribute to laser oscillation. This non-efficient use of carriers makes the threshold current density much higher than one would want it to be. Making matters worse, this limitation is exacerbated with InP based materials emitting in the 1.3 - 1.6 mm range, which is the most important wavelength domain for optical fibre communication.
Another drawback of quantum-well gain material is its asymmetric gain profile. This broadens the emission linewidth of CW lasers and increases their frequency chirp under modulation. If the well could be replaced with a superior gain material that has a symmetric gain profile, emission broadening could be fully suppressed, immediately enabling the fabrication of CW lasers with a narrow linewidth and essentially chirp-free modulation capabilities.
Ideally, an optical gain material is atom-like, with discretized energy levels and occupation restricted to the ground state. To accomplish this, energy separation between the ground state and the excited states must be large enough to prevent the excitement of carriers to these higher energies at any operational temperature. Fulfil this requirement and optical gain will peak at the ground state transition, with no carriers ‘wasted’ through the occupation of other levels. Quantum dots that exhibit atom-like behaviour can accomplish this (see Figure 1).
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The fundamental advantages of atom-like or quasi zero-dimensional gain material are well-established, and were known to developers of semiconductor lasers shortly after the introduction of quantum well materials. However, back then no-one knew how to fabricate a quantum dot laser.
A major breakthrough came in the mid-1990s, through the introduction of the so-called Stranski-Krastanov growth technique. It enables defect-free epitaxy of high-density quantum dot layers (see Figure 1 for an atomic force microscopy image). Unfortunately, the size of the dots within these layers varies, resulting in transition linewidth broadening, due to the quantum size effect. This is a major impediment, because it increases spectral gain significantly. The bottom line is that the predicted intrinsic advantages of ideal quantum dot lasers are masked by the imperfections of nanoscale structures.
In the intervening years, the properties of quantum dot material have vastly improved. 1.3 mm GaAs quantum dot lasers were first produced at the start of this decade, and more recently our partnership between the Univeristy of Kassel and Technion has extended this technology to longer wavelengths, pioneering InP-based quantum dot lasers that operate at 1.55 mm. This material is actually better than GaAs for making quantum dots lasers, as the built in strain is just 3.2 percent, rather than 7.2 percent. This makes InP-based quantum dot lasers mechanically much more robust, and it is also possible to compensate for the compressively strained quantum dot layers with tensile-strained barriers.
Our success hinges on two major breakthroughs in InP-based quantum dot material. Firstly, we have trimmed size fluctuations. This has led to an emission linewidth for a single quantum dot layer of just 17 meV at 10 K, and a corresponding value of 30 meV for a six-layer stack used as the gain region in laser structures. Secondly, we have increased the density
of dots to 6 x 1010 cm-2.
These advances have had a strong impact on the modal gain of this class of device – our laser has produced record values of up to 14 cm-1 per dot layer, or more than 80 cm-1 for an entire structure. So high are these values that they prevent gain saturation, even in the very short laser cavities needed for high-speed devices. Another attribute is that the splitting energy in the dots is high enough to slash carrier losses that come from thermal excitation (see Figure 1).
Thanks to these superb material properties, our lasers have a far higher temperature stability than their quantum well predecessers. Operating in pulsed current mode to avoid parasitic heating effects, ridge waveguide lasers that feature eight quantum dot layers have a characteristic temperature (T0) of 136 K up to 75 °C, and 110 K up to 150 °C (see Figure 2, left).
This figure of merit, which characterizes the temperature dependence of the threshold current, exceeds that of a typical quantum well laser by factors of two to two-and-a-half. Over operating temperatures that span 20 °C to 100 °C, the external differential efficiency – that is, the slope of the curves – is essentially constant.
We have also characterised the CW output of our quantum dot lasers (see Figure 2, right). Devices with a short-cavity ridge waveguide and six quantum dot layers produce an output in excess of 35 mW at 20 °C, but are restricted to below 20 mW at 70 °C.
Our lasers have been dynamically characterized in small- and large-signal modulation. Plots of small-signal -3dB bandwidth as a function of operating temperature reveal high temperature stability of the modulation bandwidth, which is 14±1 GHz between 15 °C and 60 °C (see Figure 3). The high degree of stability stems from the high temperature stability in threshold current and the consistency in the slope of light output characteristics.
Eye diagrams for this laser have been obtained under digital modulation (an example at 30 GBit/s is shown in the inset of Figure 3). The eye closes at 36 GBit/s, which is a record for any quantum dot laser.
Manufacturers of high-volume, high-performance components for data-com applications spanning 1.25 - 1.65 mm will take note of this record value, because it demonstrates that our lasers can fulfil the demand for 25 or 28 GBit/s directly modulated data channels without temperature control. Freedom from temperature control and operation at elevated temperatures are highly valued, because they enable our devices to be deployed in low-cost, small form-factor optical cables using course wavelength division multiplexing or simple multi-wavelength pulse amplitude modulation (PAM4) formats.
Encouragingly, the best is still to come for our quantum dot lasers, because they have the potential for even high temperature stability and far faster modulation speeds. Through optimization of the epitaxy and laser design, inhomogeneous gain broadening should reduce, improving spectral gain by a factor of three to four. In turn, the higher gain should lead to doubling of the modulation bandwidth, so that direct modulation rates exceed 60 Gbit/s. Temperature stability should also improve, thanks to a narrowing of the gain peak and an increase in the energy splitting to the excited states.
To realise high-volume production, we must combine our technology with that of silicon, so that these devices are manufactured on high-yield, large-wafer fabrication facilities that are already used in silicon photonics. Up until now, the most common approach for hybrid integration of III-V components involves the construction of individual devices using flip-chip technology. However, die and wafer-bonding techniques are under development for devices with more complex functionalities, such as multi-channel transmitters. An example of this approach has been undertaken in the European project SEQUOIA, which includes members of our team at the University of Kassel. Part of this programme involves the development of bonding processes for GaAs- and InP-based quantum dot laser materials on silicon photonic chips (see Figure 4 for an example of wafer and die bonding).
One of the goals for SEQUOIA is to demonstrate data-com transmitter chips for 400 Gbit/s point-to-point communication. Efforts will involve two approaches: 16 directly modulated 25 Gbit/s channels, and a quantum dot, laser-based frequency comb with a 16 channel on-chip ring modulator array. On-chip integration will be with either silicon-based photonic circuits, or together with driver or logic circuits. Regardless of the approach, it is imperative that the process yields a highly reliable, temperature-insensitive, high-performance light source. Our latest quantum dot laser material is better suited to fulfilling those demands than its quantum well counterparts.
As previously mentioned, one of the merits of atom-like gain material is its symmetric gain function (see Figure 1). Ideally, this results in emission with an incredibly narrow linewidth, which can be quantified by a Henry linewidth enhancement factor, a, of zero. In comparison, the value of a in a standard quantum well laser is 3-4, which broadens the linewidth by about an order of magnitude. This indicates that while the linewidth of a III-V laser depends on features of its design – such as the cavity length, coupling strength of feedback gratings and quality factor of the cavity – it can be trimmed by an order of magnitude by substituting a quantum well active region with an appropriate quantum dot structure.
Measurements on our 1.2 mm-long distributed feedback lasers with two quantum dot layers show that as injection current increases to 200 mA, photon density in the cavity rises and linewidth falls to about 110 kHz (see Figure 5). This laser, which has lateral index gratings on both sides of its ridge waveguide, can produce an output power exceeding 9 mW, and realise a stable side-mode suppression ratio of more than 40 dB.
The narrow linewidth above 200 mA makes this laser an attractive candidate for higher order modulation formats in coherent communication, such as quadrature phase shift keying or quadrature amplitude modulation (QAM). With these technologies, the number of detectable symbols depends on the frequency resolution of the reference laser. In high-capacitance transmission lines, modulation formats up to 256 QAM are used – they must distinguish 256 states and allow parallel transmission of 8 bits per channel. Further increases in the data transmission rate can come from the Baud rate and the number of wavelengths used in a dense wavelength division multiplexed system. However, for the latter, the reference laser must to be precisely tuned to each channel wavelength, which needs a widely tuneable, spectrally pure light source.
Working within the European EUREKA project SASER, we developed a quantum dot laser that is based on a tuneable light source and utilises the intrinsic quantum features of this zero-dimensional gain material. Our integrated optoelectronic light source contains a distributed feedback laser array with different grating periods (see Figure 6). Applying thermal tuning to this chip – that features a quantum dot semiconductor amplifier section to equalise the power levels before boosting them higher – allows emission to cover the entire C+ communication band between 1525 and 1570 nm (see Figure 7). Following amplification, the emission linewidth is about 130 kHz, with a value that depends on the laser current, but is independent on the SOA current.
Given the complexity of this chip, which is still in its infancy, it is not surprising that it suffers from many imperfections, including high losses in the coupling region. However, it demonstrates the potential of our quantum dot material, which can accomplish a reduction in emission linewidth compared to quantum well gain material without being fundamentally restricted in chip design or laser performance.
The upshot of all our success during the last few years is that quantum dot lasers are now competing with quantum well incumbents in many key areas, while exceeding them in others. Our lasers are comparable to quantum well designs in terms of threshold current density, external differential quantum efficiency, modal gain and output power; and thanks to the atom-like gain material, they have the upper hand in temperature stability, dynamical properties, noise and linewidth.
Armed with all these attributes, InP-based quantum dot laser material seems to be the leading candidate for wafer or die bond processing in hybrid integrated silicon-photonics technology, in particular in regard to reliability issues.
The authors we would like to acknowledge the financial support by the European Commission and the German Ministry of Education and Research (BMBF) through the SEQUOIA and SASER projects, respectively, as well as the Israel Science Foundation.
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There has been a rapid and strong wave of support responding to PhotonDelta’s call in the December issue of PIC International magazine for more long-term technology planning. Jonathan Marks updates on reaction to the roadmap proposal and announces key dates for your diary.
PhotonDelta and AIM Photonics are now working together to organise the first meeting of the World Technology Mapping Forum. The goal is to produce the first International Photonic Systems Roadmap, looking ahead to global technology needs in 2030 and beyond.
Michael Lebby, a well-known figure in the photonics community, is heavily involved in preparing the ground for an informed conversation.
“I expect the gathering in June in The Netherlands to explore the opportunities that we can't see today which will be commonplace in a decade. This long-term roadmapping discussion is essential for government, research and industry to work out where they want to invest precious finances in new technologies over the next 10-15 years.”
“This forum is very different from product roadmap discussions. The time line is much longer. Datacentre companies have been saying for the last few years that they want to achieve a cost structure of US$1 per Gigabit at 400 Gb/sec for a 2 km long fibre optic link. So, if you have a fibre optic link connecting two switches in a datacentre, then these companies are saying they only really want to pay US$400 to install a transmitter/receiver at either end.”
“If you put that data into a roadmap scenario and bring the experts together, then you start asking the question how can we get the technology to work and what needs to happen to bring the price down to US$1 per Gigabit and keep the customer happy. It may be that you hit a brick wall and achieving that goal is not achievable, but in doing so you will uncover a lot of interesting challenges.”
The organisers are now reaching out to bring a broad-range of senior photonics experts together in a trusted, non-competitive environment and let them interact with (potential) customers of their technologies. Good roadmaps pinpoint the most crucial technologies and define the key metrics which need to be achieved to pave the way for volume solutions.
“A decade from now we’re going to have sensors everywhere. They’ll measure a lot of things not possible today; air-quality, lifestyle, autonomous vehicles. And expect billions of sensors, each of which needs to be connected yet remain secure. How do we bring the costs down so they become ubiquitous? This is something that we need to get to grips with in the road-mapping discussion.”
KG Charles Harris is the CEO of Quarrio, an artificial intelligence enterprise in Berkeley California.
“Photonics development is crucial to us. The way that artificial intelligence works today is fundamentally different from the way it needs to work tomorrow. Photonics is an instantaneous technology. Light is already starting to impact the basic computing infrastructure, responding to market demands for ever faster processing (think high-frequency trading). Companies such as IBM, Intel, Microsoft and Google have the deep pockets to invest in the high-volume chips. But there is also a role for small scale-up enterprises building specific applications using systems built directly on a dedicated photonics chip.”
“Many of today’s technologies like the search engine, satellite communication, today’s high-speed Internet, the relational database, or modern voice controlled services like Siri, Cortana or Alexa owe their existence to long-term planning conferences organised decades ago.”
DARPA, a defense agency run by the US Military, is credited with the early development of the Internet. The International Technology Roadmap for Semiconductors (1998-2016) was also a notable initiative, bringing together just under 1000 global companies to map the next 15 years. That contributed to the development of smart chips in consumer tablets today containing over 2 billion transistors. However, semiconductor innovation is slowing as industry faces fundamental technological limits.
“Unfortunately, we have become more focussed on just applied research and much shorter term thinking. If we in the West want to compete, keep up or collaborate with China, we must think longer-term. They have 5, 15, 50 year plans - all in technology. In the 1990’s, China was mainly the source of low-level technology and products. Today their companies compete with Cisco, Google and Apple.”
“But still, no single person or country has a key to all the answers. We need to collaborate, because a true mixing of the minds will create results that benefit everyone.”
Ewit Roos, Managing Director of PhotonDelta will elaborate on what mapping means to industry in his keynote at PIC International at 12.40 on March 7th.
He explains that as photonic integrated circuits using indium phosphide, gallium nitride and silicon nitride ramp up in a global market, many new players are entering the field. They take a non-traditional approach to working.
“Coupling optical technologies with electronics offers paths to next generation smart devices that are 1000 times faster, process 1000 times more data and yet use much less energy. The outcome of the World Technology Mapping Forum is going to generate a very useful fact-based investment guide for the future.”
The three-day gathering will be held from June 14 -16, 2017 in 's-Hertogenbosch, in the heart of the Netherlands high-tech sector. The organisers are fortunate in having the full support of the regional government of North Brabant, who realise the significance of this gathering of technology leaders. The workshop mapping sessions will be held in private, to encourage frank and meaningful discussion. Attendance is by invitation only. If you believe you could contribute to the high-level technical discussion, you are invited to get in touch with the organisers before March 15th 2017. Please mention you saw this article in PIC International magazine.
To get in touch, send a note to firstname.lastname@example.org
It’s time to pack your conference bag and get ready for one of the most eagerly awaited industry events on the photonic integrated circuit calendar. James Tyrrell, programme manager of the 2017 show, highlights the many opportunities for attendees.
With the full agenda for PIC International 2017 unveiled and available to download, it’s time to start planning your two-day conference schedule. And if you haven’t got a ticket then hurry. Only a handful of places remain, which is no surprise given the rising interest in photonic integrated circuits (PICs), the solutions these devices provide and their market potential.
PIC International offers is a rare opportunity to discuss all aspects of the technology in-depth with leading designers, developers, manufacturers, assembly and packaging experts gathered in one venue. Plus, the exhibition is a great place to meet with equipment providers and discover the latest production solutions, as well as to talk about future prospects. And then there are also the PIC Awards to look forward to - celebrating the latest industry highlights and recognizing the contributions that have paved the way for today’s optical chips.
The five themes of this year’s show build up a highly-detailed picture of progress in photonic integrated circuits, beginning on day one with ‘Supporting data centre growth’ - a significant market opportunity for PICs. Companies presenting include Seagate Technology, IBM and Intel - to name just a few of the big names attending in 2017. The morning session continues its focus on areas that are well-suited to the elegant solutions offered by optical chips, examining application examples in sensing and medical fields. Highlights include a progress update from imec on tailoring PICs for use in the life sciences, as well as industry insight into the evolution of PIC-based sensors.
Having taken a first look at the applications landscape, the agenda then dives into PIC design, manufacturing and packaging - showcasing advances in turning device concepts into volume products. Solving bottlenecks in PIC development and manufacturing will be critical to the greater adoption of devices and the presentation schedule highlights progress in automation from both design and production perspectives.
Concluding day one are the PIC Awards and dinner, a valuable opportunity to follow up on the day’s talking points and to make contact with some of the industry’s brightest stars.
On day two, the discussion turns to materials and platforms and brings expert opinion from leading labs worldwide on solutions for tomorrow’s PICs to take device performance to the next level
Telecoms has in many respects led the way for the commercialization of PICs and developers have a rich knowledge in deploying integrated photonics. Saving (what could be) the best until last, the final theme of this year’s show is ‘Leveraging PICs in long-haul and metro networks’. With a packed line-up of industry big names including Infinera, Oclaro, Acacia, Huawei and Ciena, this afternoon session gives delegates the perfect opportunity to tap into a wealth of experience and maximize the value of attending PIC International 2017.
Also, on that note, don’t forget that the conference ticket also provides access CS International (now in its 7th year) and a brand new event - IoT International. Both shows are co-located with PIC International 2017.
About the author
James Tyrrell is a freelance science and technology writer working with Angel Business Communications on PIC International magazine and its sister conference PIC International.
Ségolène Olivier, an R&D project leader on advanced silicon photonics components at Leti, reviews some of the latest platform enhancements towards more compact, high-performance and power-efficient PICs for telecom networks and data centre applications.
Since the 1990s, from the first submarine optical cable to fibre-to-home deployment and the multiplication of mega data centres, light has become the ultimate medium for high-speed optical communications. Indeed, optical interconnects are progressively replacing their electrical counterparts for shorter and shorter distances.
With the huge increase in data transfer and the number of networked devices, data traffic has exploded in the past decade to reach the zettabyte range, meaning that several billion terabytes of data are exchanged each year. Moreover, this amount is expected to double every two years. This huge traffic explosion creates an unprecedented challenge for both telecom and data centre networks to manage.
Telecom networks require high-performance complex technologies optimized for high spectral efficiency and high bandwidth, due to the cost of deploying the equipment. Data centres, often featuring tens of thousands of servers, will need high-volume, cost-effective and low-power-consumption solutions to connect an extremely large number of ports with a lot of flexibility to allocate jobs to any server at any time. Both telecom and datacom networks will require optical transceivers that combine higher performance with smaller form factors, raising the need for high-level chip integration rather than for discrete components.
Silicon photonics on a silicon-on-insulator (SOI) platform has emerged as the most promising platform to offer high-volume, low-cost and high-speed interconnect solutions. Leveraging the fabrication infrastructure and processes of the CMOS industry, silicon photonics offers the possibility to integrate a high number of optical functions, such as passives, modulators and photodetectors, operating at high date rate on a single chip. The operation speed can be further increased by implementing wavelength-division multiplexing (WDM) and advanced modulation formats, making silicon photonics technology scalable for a Tb/s aggregated data rate. In addition, silicon photonics integrated circuits naturally lend themselves to 3D integration with their driving CMOS electronics for high-performance, low-cost and small form-factor transceiver modules.
A schematic of a multi-channel transceiver is shown in Figure 1. On the transmitter side, several lasers at different wavelengths with controlled polarization are coupled to several on-chip modulators with their driving electronics. The different wavelengths are gathered into a single waveguide by a multiplexer and then sent to an optical fibre by means of a single polarization grating coupler. On the receiver side, light with arbitrary polarization is coupled from the fibre to the silicon photonic circuit thanks to a polarization-splitting grating coupler, and then sent to a de-multiplexer. This component separates the different wavelengths to different waveguides and photodetectors connected to their electronics, which converts the generated photocurrent to usable voltage. A full library of high-performance silicon photonics components has been developed worldwide to operate at a speed of 25 to 50 Gb/s to build such WDM optical links. Silicon modulators are based on the plasma dispersion effect, in which the charge variation induced by an applied voltage in a PIN, PN or MOS junction is converted to intensity modulation in a Mach-Zehnder interferometer or resonant ring structure, while photodetectors are based on a germanium PIN-junction integrated on silicon.
Silicon photonics therefore offers a very attractive scalable platform to fulfill the demand of next-generation telecom and datacom interconnects. Complex photonic circuitry can be built to transmit and to detect advanced modulation formats such as polarization diversity multiplexing quadrature phase-shift keying (PDM-QPSK) for coherent transmission. This advanced modulation format, using both multiple phase levels and polarizations of the light wave to code the binary signal, is expected to be used in metro networks and inter-data-centre links. It allows systems to reach data rates of 100 Gb/s per wavelength with hardware bandwidth of 25 GHz and an assembly process far easier than existing technologies combining discrete parts. Such silicon photonics-based coherent transceivers are already commercialized (Acacia Communications).
A second advantage of silicon photonics is the possibility to manage links in the kilometric range to connect switches in data centres using WDM. This extends the aggregated bandwidth and reach of today’s optical links in data centres, which rely on VCSEL-based transmitters and intrinsically limited multimode fibres. As a result, several commercial products for data centre applications have recently emerged, with a data rate of 100 Gb/s per module, such as 100G LR4 CPAK (Cisco), 100G QSFP28 (Mellanox Technologies) and 100G CWDM4 QSFP28 (Intel).
Thanks to the scalability potential of silicon photonics, terabit-class modules are expected in the near future, following the roadmap for Internet switches, with bandwidth density as high as 40 Gbps/cm2 and reduced power consumption. However, until now, the laser source has remained separated from the rest of the chip, leading to high-cost, high packaging complexity and unavoidable coupling losses to the rest of the circuit, limiting the reduction of power consumption. The use of external lasers is also an impediment for practical scalability to much more complex photonic circuits with a very high number of integrated components.
The heterogeneous integration of III-V semiconductors with silicon by using direct bonding techniques is a promising short- and medium-term solution. This approach exploits the highly efficient light-emission properties of III-V semiconductor materials, such as compounds based on GaAs and InP, as well as the compact and low-loss photonic circuits on silicon.
The architecture of a hybrid III-V-on-silicon laser is illustrated in Figure 2. Light is generated in the III-V material, which acts as a very efficient gain medium and is then coupled down through the SiO2 spacing layer to the silicon circuitry. All the elements of the laser cavity, except the gain medium, are fabricated in silicon, which enables higher performance thanks to the maturity of silicon fabrication processes, namely the cavity mirrors – for example, Bragg mirrors or distributed feedback (DFB) gratings – and additional filtering elements. Fibre couplers are also fabricated in silicon for light output of the lasers. The challenge for such hybrid lasers is to efficiently couple light from the III-V material to the silicon. For this purpose, adiabatic coupling schemes with optimized waveguide shapes have been developed, as illustrated in Figure 2.
Leti has developed this hybrid III-V/Si platform using a direct-bonding technique. In this approach, illustrated in Figure 3, unstructured InP wafers or dies are bonded with relaxed alignment tolerances, epitaxial layers down, on a SOI wafer containing waveguide circuits. Afterwards, the InP growth substrate is removed and the III-V epitaxial film is processed by a succession of photolithography, etching and deposition steps.
This integration of lasers on silicon for various communication applications in collaboration with III-V Lab and in the framework of the French IRT Nanoelec project has produced noteworthy results. In the following section, we present some of our recent advances on laser performance improvement and on the integration of lasers with other silicon photonic elements such as modulators.
High-power tunable lasers are required for telecom applications at 1550 nm wavelength using dense wavelength division multiplexing (DWDM). The laser developed by Leti and III-V Lab and illustrated in Figure 4 (left) is comprised of a hybrid III-V on Si gain section, of Si back and front distributed Bragg reflector (DBR) mirrors to form the laser cavity, a filtering system of two ring resonators within the cavity and a fibre grating coupler at the output. The two ring resonators have a slightly different radius to exploit the Vernier effect to ensure a single-mode behavior of the laser over the whole gain spectral range. Thanks to metallic heaters integrated on top of the ring resonators, tunability over a wide wavelength range of 40 nm has been achieved, together with an excellent monomode behavior and a power level of several dBm, close to that of bulk InP lasers. Compared to discrete bulk InP lasers, such hybrid lasers lend themselves to a higher degree of integration with wavelength lockers or chirp-management components, for example. Direct modulation of these tunable lasers has been demonstrated at 10 and 25 Gb/s, which also makes them excellent candidates for access networks.
Hybrid III-V-on-silicon lasers have also been successfully integrated with silicon Mach-Zehnder modulators for data centre applications at 1310 nm wavelength. Our integrated single-channel transmitter developed within the IRT Nanoelec project and pictured in Figure 4 (right) has been demonstrated at 25 Gb/s operation speed over a distance of 10 km. The hybrid III-V-on-silicon integration technology also offers new options for modulation and detection. Indeed, other active devices such as electro-absorption modulators, photodiodes and light amplifiers also have been realized. Following this approach, a transmitter based on the integration of a hybrid DFB laser, a III-V/Si hybrid electro-absorption modulator and a hybrid III-V/Si semiconductor optical amplifier were demonstrated at 32 Gb/s operation speed.
Beyond this demonstration, one of the attractive features of heterogeneous integration using III-V dies is the wide choice of gain materials, allowing separate optimization of lasers, III-V electro-absorption modulators and photodiodes to build high-performance, high-speed and low-power-consumption transmitter circuits.
The two examples presented above illustrate the exceptional performance of hybrid III-V-on-silicon lasers for fully integrated circuits. Their technological integration scheme can be adapted to extend the compatibility of hybrid lasers with industrial silicon-photonics fabrication lines of photonic integrated circuits, including passive and active devices with several standard front-side metal interconnect levels.
Leti has developed for the first time a back-side integration process on SOI wafers (Figure 5), compatible with existing silicon photonics fabrication flow at STMicroelectronics’s Crolles facility and compatible with electronic-photonic integration on the front side.
Laser integration in silicon photonic integrated circuits is key for reducing both power consumption and cost and to derive the benefits of the full scalability potential of silicon photonics technology to build complex photonic circuits for next-generation metro and access networks, data centres, high-performance computers and optical networks-on-chip connecting different processor cores.
The introduction of new materials in the silicon photonics platform will improve its performance and its flexibility, opening it to a wider variety of applications. Introducing a silicon nitride optical layer, whose refractive index is much less sensitive to temperature than silicon, is another example of silicon photonics platform enhancement. This property can be exploited to build nearly thermally insensitive wavelength multiplexers (MUX) required for low-cost coarse wavelength division multiplexing (CWDM) applications, in which the photonic integrated circuit will remain uncooled. A third example is the hybrid integration of GaAs-based compounds to build non-linear optical devices, such as multiple frequency-combs, paving the way for petabit/s data traffic.
Beyond optical interconnect applications, new areas will be explored such as sensors for the Internet of Things, imagers for augmented reality and bio-photonics for healthcare. These new applications of silicon photonics will require integration of new optical functions with new materials.
Ségolène Olivier specializes in silicon photonics at Leti where she is head of a project developing integrated transmitters on silicon for WDM applications in collaboration with III-V Lab. She is the author or co-author of more than 80 papers in scientific journals and international conference proceedings and has contributed to several patents.
André Richter, Sergei Mingaleev and Igor Koltchanov of VPI Photonics discuss the power of a layout-aware schematic-driven design methodology for accelerating the application of integrated photonics.
Despite impressive advances in integrated photonics technologies, costs associated with the design and fabrication of photonic integrated circuits (PICs) are still several orders of magnitude higher than those for their microelectronic counterparts, which limits the rapid application of PICs in many areas. The need to reduce these costs has been a major driving force for integrated photonics development during the past few years. So why not directly adopt the well-proven methodologies from electronic design automation (EDA)? While similar to electronics, the key for cost reduction lies in the introduction of standardized process design kits (PDKs) and a generic foundry model. However, recent design trends show that dedicated photonic design automation (PDA) tools – closely integrated with EDA tools – are necessary to address the specific PIC design needs.
The fundamental difference between the design processes for photonics and electronics is caused by the double nature of optical waveguides. In some cases, they just route optical signals between building blocks (BBs), comparable to electrical wires in electronic circuits. This is when waveguide properties might not be important. In other cases, however, waveguides determine interference conditions between signals in different optical paths. Their properties are of crucial importance in such cases and should be known and already taken into account at the start of the circuit design. Unfortunately, there is no clear separation between those two types of cases. As the designed PIC grows, adding new couplers between reflective parts may turn any connecting waveguide into a functional one. Functional waveguides often serve as connectors of other components, so their dimensions are restricted not only by the desired functions, but also by the geometrical requirements of an adequate layout connectivity. Consequently, the PIC design process cannot be separated so easily into two distinct stages as is possible in the case of electronic circuit design. This is outlined in more detail below.
Utilizing the standard schematic-driven design approach, the circuit layout is fully determined by the connectivity between ports of neighboring PDK BBs, which requires that the layout of any individual BB is completely defined by its parameters. This allows circuit simulations of the designed PIC to be performed immediately, since the compact simulation model of each BB is known at any design step. However, due to the twofold nature of optical waveguides in PICs this approach is often not feasible. For instance, even the design of a simple Mach-Zehnder Interferometer (MZI) with a given free-spectral range (FSR) around a nominal center frequency sets a number of functional and geometrical design requirements on the two optical waveguide arms forming the MZI, which leads to deriving and solving a cumbersome set of nonlinear equations. In practice, attempts to design more or less complex PICs employing the standard schematic-driven design approach can result in very time-consuming back and forth iterations between the circuit simulator and layout tool. Moreover, design tasks such as device performance and yield optimization cannot be automated and thus become merely unmanageable.
For a number of applications, the problems outlined above can be solved by employing a layout-driven design approach. For example, dedicated photonic layout design tools (such as OptoDesigner by PhoeniX Software and IPKISS by Luceda) provide advanced scripting capabilities with support of an easy netlist-based PIC design process and immediate access to relative and absolute locations of any BB ports inside the circuit netlist. Moreover, they provide advanced routing capabilities, including support of elastic waveguide connectors. However, accurate and efficient simulation of modern large-scale PICs with a mix of passive and active BBs requires development of complex specialized circuit simulation engines. That is why the layout-driven design approach should include a separate stage for the simulation of the designed PIC with a dedicated photonic circuit simulator. But simulations of complex non-passive circuits require embedding the designed PIC into a complex simulation framework: adding properly configured electrical and optical sources, post-processing of output signals with specialized instrumentation tools, and visualization of obtained results. Consequently, designers need again to frequently switch between a layout design tool and circuit simulator, and experience serious difficulties trying to organize automated sweeps over layout parameters or perform automated design optimization.
The layout-aware schematic-driven design methodology  represents an efficient practical solution to the issues outlined above, as it allows circuit simulation and layout design tasks to be performed simultaneously, using the same schematic capture environment. For this, a circuit-level simulator is seamlessly integrated with a layout design tool, providing designers transparent access to the capabilities of both software packages, as illustrated in Fig. 1. In particular, it becomes possible to directly specify in the circuit-level simulator physical locations and orientations of PDK BBs on the final layout. Also, the library of PDK BBs is extended with a set of elastic waveguide connectors (the same as provided by the underlying layout design tool), allowing sub-circuits having fixed locations to be easily interconnected without the need to manually solve complex geometrical problems. The circuit simulator automatically, and invisibly for users, invokes the layout design tool to determine the actual physical lengths and shapes of all elastic connectors, constructs compact simulation models for them, and after that initiates the circuit simulations. This allows the combination of graphical schematic capture, layout design with automated waveguide routing, and circuit simulations, which are currently considered separately representing a major problem for PIC designers.
As an illustration of this design workflow, let us consider the MZI design shown in Fig. 2. Problematic waveguides use elastic waveguide connectors; the physical locations and orientations of all outer waveguides are directly specified with absolute coordinates, allowing packaging requirements to be fulfilled. Finally, the physical location and orientation of the MZI sub-circuit can be specified using relative coordinates with respect to the location of the port of another block with fixed location. All of these port locations can be specified using advanced parameter scripts – so that, if required, locations of BBs can be specified after solving arbitrarily complex equations. That is, the circuit may now be designed in almost the same way as it would be designed with the layout-driven approach. Since this design is still performed in a circuit simulator environment, one can easily combine PDK BBs with any signal sources and instrumentation modules required for signal post-processing and organization of parameter sweeps and/or optimization.
Here, the Spectrum Analysis block allows transfer function spectra to be visualized, automatically extract their peak properties, and estimate and plot the device FSR. Importantly, our implementation of the layout-aware schematic-driven design approach supports automated sweeps and optimization of layout parameters. For this, the layout design tool is automatically invoked to determine the actual physical lengths and shapes of all elastic connectors at each simulation step. As an example, Fig. 2 (bottom, left) shows the dependence of MZI FSR on the bend radius R as result of an automated parameter sweep, which can be easily organized by the PIC designer by merely specifying the name and value range of the swept parameter. Also Fig. 2 (bottom, right) illustrates automated optimization of the same bend radius for a desired FSR of 200GHz. Other frequently required simulation capabilities, such as multi-dimensional parameter sweeps and optimization, combination of sweeps with optimization, sensitivity and yield analysis, as well as yield optimization can be supported with this approach as well.
In practice, the PIC design usually starts with elaborating a circuit idea – at this stage, the circuit layout is ignored, and designers concentrate on elaborating a principal scheme which enables the required circuit functionality. This stage can be addressed by a standard schematic-driven design methodology, based on the usage of standard PDK waveguides. At the second stage, the circuit layout is taken into account ensuring layout connectivity and accounting for packaging requirements. To simplify the transition from the first to the second stage, we provide the possibility to easily replace all selected standard waveguides with their elastic counterparts, and thus introducing layout flexibility which is used to optimize the circuit design and easily satisfy all packaging requirements. This is the stage where the layout-aware schematic-driven approach is most intensively used. Once the optimal circuit design is fully elaborated, it may be a good idea to “fix” its layout. For this, we provide the possibility to easily replace elastic waveguide connectors with their standard counterparts, fully preserving the optimal circuit layout. Such a circuit may now be automatically converted into a compound building block and be used as part of a more complex circuit.
Similar to electronics, the design of large-scale PICs requires splitting the whole circuit into manageable functional sub-circuits, which are possibly further decomposed into yet smaller sub-circuits and foundry-certified PDK BBs. Support of this type of multi-level hierarchy within the framework of the layout-aware schematic-driven methodology is non-trivial. Considering the design example of a cascaded-MZI demultiplexer in Fig. 3, the input optical signal is split between two cascaded MZIs, both being instances of the same user-defined parameterized compound BB CascadedMZI with only different parameter settings. The CascadedMZI block contains, in its turn, three instances of another compound BB MZI, built of fundamental PDK BBs and elastic connectors. Importantly, user-defined compound building blocks need to support the same design workflow as built-in PDK BBs. That is, they should offer the possibility to specify physical locations and orientations of their ports on the final layout. In our example, this mechanism is used to specify locations of the CascadedMZI blocks. Another important functionality is the possibility to create custom compound BBs that are described by functional design parameters rather than structural layout parameters. In the case of the MZI block in Fig. 3, we employ FSR and resonance frequency instead of specifying waveguide lengths and bend angles. This requires parameter scripting  enabling calculation of the needed waveguide dimensions by solving a system of nonlinear equations derived from a maximally compact layout condition enabling the desired FSR and resonance frequency.
As discussed above, handling the complexity of large-scale PIC designs requires the use of a layout-aware (multi-level) hierarchical methodology. However, this alone is not always sufficient – especially in applications addressing the design of large-scale optical networks on chip (NoC), as illustrated in Fig. 4. The major problem in designing such networks is given by properly interconnecting all paths between the optical switches, including the resolution of waveguide crossings. An NxN switching network requires N2 interconnections, which may be organized in different ways: minimizing the total number of waveguide crossings (thus minimizing total optical power losses), or trying to balance the number of crossings for each optical path (thus balancing optical power losses). The optimum scheme depends on the optical properties of the underlying BBs (waveguide, bend, and crossing). Therefore, the analysis and optimization of such networks requires the construction and simulation of a large number of complex circuits.
Trying to construct such networks manually (dragging, dropping, and connecting hundreds of BBs) is an extremely inefficient and error-prone process. This problem can be solved by providing support through macro scripting capabilities, which permit the placing and connection of any BB on the schematic and the adjustment of its parameters in a programmatic way. VPIcomponentMaker Photonic Circuits supports macro scripting with Python and its very powerful object-oriented programming capabilities being extended by a library of special commands addressing almost any task that can be performed through the standard user interface. The successful design of complex optical networks as shown in Fig. 4 with macro scripting requires its extension with a set of layout-aware commands, which allow physical locations and orientations of BB ports to be determined on layout, locations of waveguide crossing, and others. Enabling such standard capabilities of layout design tools in circuit simulators represents another important reason for the close interfacing between circuit simulation and layout design tools.
Consequently, graphical schematic capture and automated waveguide routing can be combined. Enabling this functionality: the circuit simulator automatically and invisibly for users invokes a layout design tool to determine the physical dimensions of elastic connectors, constructs compact simulation models for them, and initiates the circuit simulations. Importantly, the presented approach enables automated parameter sweeps and optimization even for parameters that affect the circuit layout – a task which cannot be performed by standard schematic-driven or layout-driven design approaches. Based on our experience, we predicate that, driven by the fundamental difference between electronic and photonic circuits, the future development of PDA tools will proceed further with much closer integration between circuit simulation and layout design tools than it was ever required for EDA tools.
 S. Mingaleev, S. Savitski, E. Sokolov, I. Koltchanov, and A. Richter, “Layout-Aware Schematic-Driven Design Methodology for Photonic Integrated Circuits,” European Conference on Integrated Optics, p. 21 (2016).
 S. Mingaleev, A. Richter, E. Sokolov, C. Arellano, and I. Koltchanov, “Towards an automated design framework for large-scale photonic integrated circuits,” Proc. SPIE 9516, 951602 (2015).
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Published by: Angel Business Communications Ltd, 6 Bow Court, Fletchworth Gate, Burnsall Rd, Coventry CV5 6SP. T: +44(0)2476 718970. All information herein is believed to be correct at time of going to press. The publisher does not accept responsibility for any errors and omissions. The views expressed in PIC magazine are not necessarily those of the publisher. Every effort has been made to obtain copyright permission for the material contained in this publication. Angel Business Communications Ltd will be happy to acknowledge any copyright oversights in a subsequent issue of the publication. Angel Business Communications Ltd Â© Copyright 2016. All rights reserved. Contents may not be reproduced in whole or part without the written consent of the publishers. ISSN 2398-9807