Features Editor, PIC International Magazine
In issue #2, we heard from IBM, Hewlett Packard and other major stakeholders in the data centre sector to discover how PICs are poised to deliver big gains in performance. Enabling this next generation of optical chips are a number of materials platforms - including silicon photonics (SiP), which is where issue #3 of PIC International magazine begins.
Koji Yamada, head of the Silicon Photonics Group at the Electronics and Photonics Research Institute - a division of Japan's National Institute for Advanced Industrial Science and Technology (AIST), takes a detailed look at the opportunities provided by SiP and discusses the next steps for this exciting PIC platform. And then Vladimir G. Kozlov, founder and CEO of LightCounting Market Research, updates on SiP activity in the datacoms sector and examines where solutions sit alongside more established technologies.
We interview Martin Schell -- director of the Fraunhofer Heinrich-Hertz-Institute (HHI) Berlin -- to discover more about how his team works with industry to develop promising PIC concepts to the level of manufacturing maturity.
Ramping up production requires solutions in device assembly, packaging and test & measurement. And to discuss these topics in detail, we hear from light-coupling experts at Optocap and Teem Photonics, instrument providers Yelo, and explore custom solutions offered by the Advanced Packaging Center based in The Netherlands.
Lastly, Ton Backx, CEO of PhotonDelta shares his plan to roadmap the optical technologies needed for global society two decades from now.
But that’s not all. When you dive into issue #3, don’t forget to read up on the PIC Awards 2017 - announced this month, and launched to celebrate the best of the photonic integrated circuit industry. Get your nominations in today via the PIC Awards website.
Also, if you haven’t done so already, do check out the updated speaker profiles at PIC International to catch up on the latest additions to our sister conference. The two-day show offers the perfect venue for discovering the latest industry breakthroughs and finding key contacts. I’ll be at the event both days and look forward to meeting you there.
Enjoy the issue!
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Vladimir G. Kozlov, founder and CEO of LightCounting Market Research, updates on SiP activity in the datacoms sector and looks at where this promising PIC platform sits alongside more established technologies.
Expectations for Silicon Photonics (SiP) technology bounced back up in 2016. The continuing successes of Acacia and Luxtera combined with progress reported by Intel add significant credibility to this new technology. The market valuation of Acacia exceeded $4 billion in September 2016. Aurrion – a SiP start-up – was acquired by Juniper Networks for $160 million. Huawei followed Cisco’s lead in introducing SiP modules designed in-house. All this resonates well on Wall Street and with venture capitalists.
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LightCounting remains cautiously optimistic about this new technology. Data reported by optical component and module suppliers for the first half of 2016, suggests that SiP vendors made progress in penetrating two of the fastest growing segments of the market: 100G DWDM and 40/100GbE optics.
Figure 1 shows the contribution of SiP to the total market for 100G DWDM in the first half of 2016. The share of SiP remains modest compared with Indium Phosphide and Lithium Niobade based products, but it is certainly a good start. Acacia is responsible for most of this early success. NEL started offering SiP engines along with DSP chips for 100G DWDM, opening the door for other module vendors to join the race. Cisco and Huawei unveiled internally designed 100/200G DWDM SiP modules solidifying prospects for SiP in this market segment.
Figure 1: Shipments of 100G DWDM ports in the first half of 2016. (Source: LightCounting Market Research)
The DWDM market started a transition to the 200G data rate in 2016 and 400G single wavelength ports should be introduced in 2017. SiP suppliers will have to repeat the early successes with 100G solutions at 200/400G to maintain their market positions. The other more established technologies will not give up without a fight.
Figure 2 illustrates the progress made by suppliers of SiP-based transceivers for 40GbE and 100GbE applications. This market segment includes SR4 devices based on Gallium Arsenide (GaAs) VCSELs, PSM4 and CWDM4 modules which could use either SiP or InP optics, as well as LR4 transceivers which are exclusively InP at least for now.
Figure 2: Shipments of 40GbE and 100GbE transceivers in the first half of 2016. (Source: LightCounting Market Research)
Early success of SiP in the 40/100GbE market is mostly attributed to Luxtera, but Intel and Lumentum have also made modest contributions in 2016. These three vendors are shipping PSM4 transceivers for up to 500m long connections. Intel also introduced its first CWDM4 2km reach modules, powered by SiP modulators at ECOC 2016, potentially placing 10 km reach LR4 modules within the grasp of SiP technology.
Shipments of 100GbE LR4 transceivers, used in telecom applications, were growing steadily for the last 3 years. Demand for these CFP, CFP2 and CFP4 devices outpaced supply in 2016. Shipments of QSFP28 LR4 transceivers had a better than expected start in 2016, as suppliers put more effort into shipping next generation products instead of increasing production capacity for older types of LR4. 100GbE SR4 QSFP28 was also off to a good start in early 2016. PSM4 and CWDM4 had a slow first half of the year, but shipments of these products should ramp up sharply at the end of 2016.
The stage is set for a race between GaAs, SiP and InP in the 100GbE market. The main customers have placed their bets: Microsoft is solidly in the PSM4 camp, Facebook picked CWDM4 as its favorite, Google is not crazy about PSM4, but likes all other approaches; Amazon has not revealed it’s hand yet.
LightCounting will publish an analysis of this race along with the forecast for GaAs, InP and SiP-based products for all other segments of the global optical communications market in a report titled “Integrated Optical Devices”, scheduled for publication in January 2017.
Operational excellence will be the key for suppliers. Ability to control their supply chain and cost while ramping production volumes will be critical for success. Suppliers of GaAs and InP products have a solid record of delivering on expectations in the past and not going out of business. Shipments of 10GigE and more recently 40GbE products increased ten-fold in a period of 2 years accompanied by 50% cost reduction. Can these suppliers do better with 100GbE and report higher profitability along the way?
Luxtera is the only supplier of SiP products with a record of successfully ramping production volumes in the past. Luxtera reported shipments of 1 million units of SiP optical engines in 2016. No data on cost reduction or profitability of these products is available yet. Luxtera is also using a new approach for manufacturing of 100GbE products, designed for higher levels of scalability and cost reduction.
It is still unknown how much of scalability and cost reduction SiP manufacturers can deliver and whether these will be superior to GaAs and InP suppliers. Acacia’s success is often attributed to their expertise in SiP technology, but it is just one element of the puzzle that Acacia’s management worked on for years. Being ahead of the competition with DSP chip designs, securing key customers, attracting the right talent, managing suppliers and curbing competition are all just as important. Could Acacia have done this with InP optics instead of SiP? Probably yes. Would the company’s valuation exceed $4 billion in this case? Absolutely not.
Investors crave yet unproven, but potentially disruptive technologies. Who would not like to be first to invest into Si transistors or digital cameras? Disruptive technologies of the past have been well documented by C. Christiansen. The chart from his famous book is redrawn in Figure 3, illustrating how new technologies enter the market at the low end, then improve and displace the existing ones.
The important dimension missing in Figure 3 is that transistors and digital cameras enabled fascinating new functionalities along with delivering lower cost solutions. The power of Si processors and the ubiquity of digital images are undisputable disruptions. Can SiP come close to causing this level of change?
Figure 3: Market penetration by disruptive technologies. (Source: Clayton M. Christensen, “The innovator’s dilemma”)
That is the key question and the answer is known. What remains to be seen is how long this will take. One can envision a robot able to see and process images with optical connections serving as neurons connecting eyes and brains (possibly more than two and one). The brains will be CMOS multi-core processors (Xenon v40?). The eyes will use CMOS detector arrays. CMOS seems like a good choice for optical connections.
There is also no doubt that technology will continue to surprise us, extending the horizons of our imagination. It must be a lot of fun to be a futurist. Being a market analyst is also a great occupation, but it comes with a lot more responsibility for accuracy of predictions. LightCounting is often criticised for being too conservative. This is not for lack of imagination, but rather from careful examination of the short history of our industry and the much longer histories of others.
SiP suppliers should do well in 2017. A lot of factors are in their favor. Supply chain shortages of InP and GaAs based 100GbE products is one of them. Huawei is fully committed to supporting SiP technology. Acquiring Caliopa a few years ago and developing SiP based 100G DWDM solutions are confirmations of this strategy. However, Huawei is doing even more by helping SiP technology indirectly through massive purchases of 100G optics, stretching the supply chain to its limits. It is a perfect time for a new technology to advance beyond the beach head and conquer some more of the market.
Vladimir G. Kozlov has more than 20 years of experience in optoelectronics, optical communications and market research. He has held market analyst, product development and research staff positions at RHK Inc., Lucent Technologies and Princeton University, respectively. Vladimir founded LightCounting in 2004.
Web – www.lightcounting.com
The network of Fraunhofer Institutes, which has links all over the world, explores a variety of applied research themes across a range of disciplines. James Tyrrell interviews Martin Schell, director of the Fraunhofer Heinrich-Hertz-Institute (HHI) Berlin, to discover more about its work in the area of photonic integrated circuits, and find out how his team works with industry to develop promising concepts to the level of manufacturing maturity.
To help set the scene, can you summarise the role of the Fraunhofer HHI and where it sits between academia and industry?
The Fraunhofer Society’s mission is to partner with companies to transform original ideas into innovations that benefit society. As one of 66 Fraunhofer institutes, HHI researches various aspects of information transmission, ranging from video compression over wireless networks to photonic components and networks. We derive ~50% of our budget from direct industry contracts. The majority of these contracts target a time-to-market below three years. Here, we either develop our own designs or co-design new products with industry partners. We also offer measurement and test services and prototype packaging.
Fraunhofer’s role is somewhere between academia and industry: academia often focuses on work with large potential for scientific publications. At HHI, however, a large share of our work is devoted to bringing existing concepts to manufacturing maturity. Our researchers have much experience in that due to the wide range of different products in our history. Our industry partners also have the option for pre-series production on our ISO-certified Indium phosphide or polymer lines, so that transfer to high volume lines can be pushed out to later times - when both the market success of the new product is proven and the production has reached a certain stability. Compared with industry, we focus much more on maintaining scientific excellence over several decades rather than high year-to-year revenue growth.
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When did you first notice the impact of photonic integrated circuits and how have you seen the technology progress?
From 2000 to 2002, I was product line manager for FTTH at Infineon Fiber Optics. This included BIDIs, a product that separates incoming 1550 nm light from outgoing 1300 nm light. It was first demonstrated by Infineon in the mid-1990s and contained two TO cans, a thin-film filter, a ball lens and various mechanics, which were combined in about 30 manual assembly steps. Market volume was in the 10s of millions. Over the years, a couple of companies developed photonic integrated circuits, and all failed. This made me quite skeptical when I started at HHI in 2005. Nonetheless, in 2007 we started research on a monolithically integrated 90° hybrid for coherent reception, which later turned out to be a huge commercial success. Here, discrete optics seems to be fully eliminated from the market. So, if you want to have impact with your idea for a PIC, be sure to analyse the market demand, your strengths and weaknesses, and the further evolution of the incumbent technology very carefully.
Overall, I am pretty sure that photonic integration -- sooner or later -- will dominate Telecom and Datacom. I see the largest potential for PICs to not only replace discrete optics, but also to grow the market, in 3 cm to 30 cm data transmission (where PICs could replace today’s copper solutions) and in sensor applications. The technology advancement in PIC technology in the last 5 to 10 years has been huge. The fact that there are multiple activities, which have helped to significantly lower the entry threshold for the non PIC savvy developers, is of importance too. Two prominent examples are the development of Photonic Design Kits, and the availability of multi-project wafer runs for the major PIC technologies.
What aspects of the technology is the Fraunhofer HHI and its partners working on today?
We have a couple of fundamental activities such as continually increasing the complexity of InP monolithic PICs - our most complex chip contains 8 IQ modulators, 2 AWGs, and many other components. In polymer technology, which we are using as platform for hybrid integration, we incorporate, amongst others, graphene into the waveguide for modulation and receiving. This could eventually lead to an Active Optical Printed Circuit Board, where the complete optics is hidden from the surface.
On the more applied side, we develop simple schemes for getting light into and out of PICs -- for example, to be used in silicon waveguide based disposable sensors -- and we continuously decrease the energy consumption of our communication PICs. We also work on first integrated THz emitters.
In addition, we are increasing our efforts in developing generic-foundry platforms that allow partners to design and acquire PICs at relatively low-cost and short time frame. The advantage of having a generic integration platform is that the fabrication process is already there and the partner only needs to care about the design of the PIC.
We expect that many universities, research institutes, and companies, will find this generic-foundry approach attractive for prototyping PICs for their particular application. In fact, the InP platform which has been essentially developed in the framework of the EU projects EuroPIC and PARADIGM is now being offered on a semi-commercial-foundry basis with a run-schedule that takes place four times a year.
How can developers find out more about the facilities and expertise available at the institute? And what are the options for teaming up on future projects?
Our website gives a general overview of our capabilities, although we cannot always share the latest state of research. Within HHI, Martin Moehrle is responsible for the InP platform, and Norbert Keil for the polymer platform. Both have more than ten years of experience in collaborating with industry and academic partners.
As HHI, in accordance with its Fraunhofer nature, focuses very much on applied research, we are also very interested in getting in contact with more fundamental researchers - helping them to evaluate the application potential of their ideas, and to explore the possibly of joint projects.
We would also like to collaborate with all PIC vendors, even when competing with HHI, to highlight synergies and spread the word about PIC capabilities. Whilst telecom and datacom developers nowadays are pretty aware of PICs and their potential, I believe that the sensor or medical, or other related communities are still quite unaware of PIC capabilities. Here, the PIC community should spend much more effort on outreach and education in an easy to understand form, maybe based on existing structures like JEPPIX or EPIC, and existing H2020 Coordination-And-Support-Actions like PICS4ALL and RESPICESME, targeting outreach to SMEs in non-telecom sectors.
More information –
What solutions are in the pipeline to support higher performance devices in a post-Moore era? Koji Yamada, head of the Silicon Photonics Group at the Electronics and Photonics Research Institute - a division of Japan's National Institute for Advanced Industrial Science and Technology (AIST), explores the opportunities provided by silicon photonics and discusses the next steps for this exciting PIC platform.
End of Moore’s Law in data transmission systems
Moore’s Law expresses an empirical trend in device integration in electronic circuits, such as micro-processor chips. The device integration status is defined as the number of elemental devices -- such as transistors -- integrated on a chip, which doubles every two years. However, such exponential growth defined by Moore’s law is now coming to an end, because -- ultimately -- miniaturised devices see the de Broglie wave of electrons (more details below). In other words, we are now entering the post-Moore Era.
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At the same time, we are seeing explosive growth in information systems, which is one of the major applications of electronic circuits, and improvements in their performance must continue. To cope with such an information explosion, various post-Moore electronic circuit technologies are now being developed under guidelines referred to as ‘More Moore’, ‘More than Moore’, and ‘Beyond CMOS’.
In ‘More Moore’, further geometrical integration is achieved by introducing novel materials and three-dimensional (3D) integration methods. ‘More than Moore’ is a system-on-chip (SoC) approach, where non-digital devices are implemented. ‘Beyond CMOS’ refers to devices based on novel principles, such as electron spins, and novel architectures suitable for these novel devices.
Figure 1: Trend of switching capacity in a typical large-scale datacenter.
Moore’s Law in data transmission, which is an important aspect of information systems, is also facing its end. For example, as shown above, switching capacity in a typical large-scale data centre is growing at a rate of 100 to 1000 times every 10 years1, which is overwhelming Moore’s Law in electronic circuits. Since electronic circuits are used for switching systems at present, such explosive growth will become unsustainable in the near future. In the global network system, we are also facing the end of Moore’s Law.
For more than 30 years, data transmission capacity per fibre has been increasing with a growth rate of 80% a year through various paradigm shifts in technology, such as from TDM to WDM and multi-level modulations2. However, it has now reached the nonlinear Shannon limit.
Figure 2: Trend of data transmission capacity per fibre.
In order to cope with such explosive growth in data transmission, we also need post-Moore technologies for photonics as well as for electronics - because data transmission systems consist of electronic and photonic elements. For the development of post-Moore photonics technology, the same approaches in electronics can be applied, and silicon photonics provides a platform for post-Moore photonics.
Silicon photonics as a post-Moore photonic technology
More Moore: further geometrical integration (two-dimensional)
Thanks to the very strong optical confinement ability of silicon photonics technology, photonic circuits can be miniaturised considerably, and data transmission capacity per unit chip area can be increased. An example is an integrated WDM receiver chip consisting of multi-channel wavelength filters, photodiode (PD) array, and electrodes for signal output. By using silicon photonics, an arrayed-waveguide-grating (AWG) wavelength filter, which is a standard multi-channel wavelength filter, can be miniaturised to 1-mm square. Moreover, germanium PDs and through-silicon via (TSV) electronic wiring can be scattered over the whole the chip.
Figure 3: Estimated chip area of integrated WDM receiver sub-assembly.
Therefore, as shown above, the required area of a 100-ch WDM receiver chip will be reduced to 1 cm2, which is 1/100 of the area of chips based on conventional technology. Assuming PD operation at 25 Gbps, total capacity will reach 2.5 Tbps/cm2. In parallel transmission systems, where no wavelength filter is required, total bandwidth can be increased up to 30 Tbps/cm2 3.
Spatial division multiplexing (SDM) can also be categorised as two-dimensional geometrical integration. By using silicon photonics technology to make ultra-small optical coupling structures within the area of a fibre core, highly integrated SDM modules consisting of an SDM fibre interface and optical processing circuits can be constructed4.
More than Moore: photonics-electronics SoC
Integration with electronics is the most impactful post-Moore technology for photonic circuits. In particular, integration with modulation drivers, transimpedance amplifiers for PDs, and various control circuits on a silicon photonics chip can significantly reduce the size of photonic-electronic integrated modules. Moreover, since electronic circuits can be placed very close to photonic devices, high-frequency performance can be significantly improved5.
Figure 4: Photonics-Electronics convergence. (a) monolithic and (b) TSV-based hybrid integration.
Since silicon photonics is based on silicon electronics technology and the silicon platform is reliable and robust, electronic circuits can be integrated by both monolithic and hybrid approaches. Concepts of such photonics-electronics convergence can be seen above. The monolithic approach is very attractive from the viewpoint of ultra-high-volume production, and some short-range data transmission modules have already been commercialised6.
However, we must consider that device performance might be degraded because of narrow margins in the fabrication process for photonics-electronics convergence. For example, in monolithic photonics-electronics convergence, the dark current of germanium PDs is likely to increase. Moreover, typical CMOS electronics technology cannot provide the high-speed electronics required for high-bit-rate optical data transmission.
For improving device performance both in photonic and electronic circuits, the hybrid approach is attractive. Since both types of circuits can be fabricated by their respective optimised fabrication process, high-performance photonics-electronics convergence can be achieved. Hybrid integration is performed by using various wafer-bonding/die-bonding techniques with TSV and micro-solder bump technologies7. Since hybrid integration technology is a kind of 3D integration technology, it can also contribute to geometrical integration in the More Moore approach.
Novel-principle devices and architectures: replacement of electronics with photonics
Since current optical fibre transmission systems show excellent performance, we currently have very small margins for novel-principle devices. However, if we consider data transmission systems as a whole, replacing electronic circuits with photonic ones corresponds to an approach for implementing novel-principle devices and architectures. This approach can be seen in the dynamic optical path network (DOPN) using large-scale optical switch matrixes8,9. Conventional switching systems are made of electronic devices, where numerous small packets are independently routed to a number of unspecified terminals. Thus, power consumption for the switching increases proportionally to the data traffic.
Figure 5: Dynamic optical path network.
This conventional packet switching scheme, however, is not suitable for the transmission of bulky video data to specified terminals, which has been a dominant factor in the recent traffic increase. In the DOPN, as shown above, dedicated optical transmission channels are temporarily constructed by an optical switching matrix. Since packet switching is not utilised in the DOPN, the power consumption for bulky data transmission can be greatly reduced. Recently, a DPON field trial using a silicon-photonics-based optical switch matrix has been carried out8.
Evolution of silicon photonics
As mentioned, silicon photonics technology provides immediate solutions for data transmission systems in the post-Moore era. However, to deal with the expected increase in traffic in the future, silicon photonics itself must evolve much further. This is because there are serious obstacles to further performance improvement and miniaturisation.
One hurdle is the severe fabrication tolerance in silicon photonics, which is a fatal problem. Typical fabrication errors in thickness and width of Si waveguide cores are nanometres in scale. Since a silicon waveguide is very small, such errors can result in large crosstalk and strong polarisation dependence, which significantly degrade performance10.
Nonlinear effects in silicon waveguides are also serious problems in practical applications. Silicon has a large nonlinear coefficient, which is about 100 times larger than that of silica. Moreover, the optical field size in a silicon waveguide is extremely small. Thus, nonlinear effects, such as four-wave mixing and two-photon absorption, are greatly enhanced. The resulting large channel crosstalk and poor power tolerances significantly degrade device performance.
Poor carrier mobility in silicon is also a serious obstacle to achieving ultra-high speed device operation of over 40 Gbps.
Figure 6: End of miniaturization scaling.
But what about the end of Moore’s Law in silicon photonics? As discussed earlier, Moore’s Law in electronics is ending because device size has reached the wavelength of the de Broglie wave. Referring to Figure 6(a) -- for example -- as an electronic quantum well becomes thinner, the number of energy levels decreases. Eventually, the number is reduced to a single energy level, and this is the end of miniaturisation. The critical thickness is about 10 nm. Any thinner and electron confinement becomes very weak and the device will not work well.
The same analogy is applicable to optical waveguides, as shown in Figure 6(b). In other words, a single-mode waveguide, whose core size is comparable to the optical wavelength, is the end of miniaturisation. Any smaller and photon confinement becomes very weak and the device will not work well. The critical core size is about half of a micrometre for infrared transmission in the 1.55-µm telecommunications band. Since the single mode waveguide has been the most essential element in silicon photonics, Moore’s Law has already ended.
Through these discussions, we cannot help but conclude that silicon photonics requires post-Moore technology, and -- we believe -- three approaches in the development of post-Moore electronics can be applied here again for the development of post-Moore silicon photonics technology.
More More: further geometrical integration (3D)
For 3D photonic integration, backend photonics is a promising technology. Backend photonics is a performance-assisting technology using additional waveguide systems made of various materials. The requirements for the additional waveguide systems are 1) a low-loss and compact photonics system comparable to the silicon photonics system; 2) functionalities comparable to those in the silicon photonics system; 3) low-loss interlayer coupling between the additional waveguides and silicon waveguides; and 4) the ability to fabricate the additional waveguide system without damaging the silicon photonic system underneath it. In other words, the additional waveguide systems should be constructed by using the backend fabrication technology for silicon semiconductors, which is the reason we refer to the additional waveguide systems as backend photonics.
Figure 7: Integration density and fabrication tolerance in AWG wavelength filters. (200 GHz x 16 ch, neighbouring channel crosstalk < -20 dB)
Silicon-nitride-based materials, such as SiOx, SiON and SiN, are promising for backend photonics. The most attractive feature of these materials is that their refractive index can be largely tuned11. These materials cover a wide refractive index range, and optical waveguides using these moderate-index materials would significantly relax fabrication tolerance. The above chart shows the estimated integration density and fabrication tolerance as a function of refractive index contrast of a waveguide. Using moderate-index materials, fabrication tolerance is significantly relaxed while keeping still high integration density.
Table 1: Nonlinear and thermo-optic coefficients of Si and backend photonics materials
Table 1 shows nonlinear coefficients and thermo-optic coefficients of such materials. These coefficients are less than one-tenth of silicon’s. Recently, low-loss interlayer coupling structures have been developed using inverted tapers12,13. By using PECVD technology, the deposition temperature can be reduced to less than 350 degC, which would not damage the silicon/germanium devices underneath the additional waveguide system.
This silicon-nitride-based backend photonics technology has been used to develop low-crosstalk high-resolution AWG wavelength filters and integrated them with silicon-based modulators and germanium-based PDs on a silicon photonics platform14,15.
More than Moore: heterogeneous photonic SoC
The additional waveguide system can integrate various additional photonic functionalities on the silicon photonics platform, because it can increase the degree of freedom in device design. For example, by using silicon-nitride-based waveguides constructed on silicon waveguide systems; polarisation manipulation16,17 and fibre-mode MUX/DEMUX18, have already been demonstrated. Because of material incompatibilities, these functionalities were constructed outside the silicon photonic chip by using bulky conventional optical components.
Novel-principle devices: restarting Moore’s Law
As mentioned above, the core size of a silicon waveguide cannot be reduced to less than a half of the wavelength, and Moore’s Law has already ended in silicon photonics. However, we know that radio waves, which have metres of wavelength, can be confined in a centimeter-diameter cable. Radio waves are confined as a TEM-like wave supported by surface electron density waves in metals. Here, recall that the miniaturisation limit of electron density waves is determined by the de Broglie wavelength, which is around 10 nm. Thus, we can restart Moore’s Law in photonics. Roughly speaking, a photonic system based on such a metallic confinement is referred to as plasmonics.
Figure 8: Structure and optical mode field of plasmon waveguide.
The above schematic shows a photonic waveguide based on plasmonics on an Si photonic platform. The optical field is confined in a 100-nm-wide gap between two metallic plates. By filling this gap with electro-optic (EO) polymers and applying voltage to these metallic plates, we can change the refractive index of the EO polymer. Thus, we can construct a very compact optical phase shifter, which is a fundamental element of optical modulators.
Recently, such a plasmonic-polymer waveguide system has been used to develop Mach-Zhender interferometer optical modulators19. Since the gap is very narrow, the electric field in the gap is very strong and the modulation efficiency becomes extremely high. For example, the voltage-length product -- which is a measure of the efficiency of phase shifters -- reaches 0.006 V.cm, which is less than 1/100 of that of a typical silicon modulator. Thus, a device a few tens of micrometers long can function as a modulator with practical modulation depth, and such a small device can operate at very high frequencies of over 100 GHz. Such plasmonic devices would be a significant breakthrough in the post-Moore photonics technology.
Moore’s Law in data transmission systems is nearing its end, and we need post Moore-photonics technology. In the development of post-Moore photonics technology, we can apply the same approaches that have been established in electronics, and silicon photonics can provide immediate solutions for post-Moore photonics technology. However, we must note here that silicon photonics itself requires post-Moore technology because of the quantum limit in miniaturisation and poor material characteristics. Here again, the same approaches established in electronics are applicable to post-Moore silicon photonics with the help of backend photonics and plasmonics.
Koji Yamada is head of the Silicon Photonics Group at the Electronics and Photonics Research Institute - a division of Japan's National Institute for Advanced Industrial Science and Technology (AIST). Key themes of his group's work include the research and development of advanced silicon photonics devices.
References and further reading
 A. Singh et al., Proc. annual conference of the ACM Special Interest Group on Data Communications (SIGCOMM 2015), London (2015).
 D.J. Richardson, Science 330, 327 (2010).
 Y. Urino et al., Proc. ECOC 2013, Mo.4.B.2F, London (2013).
 C.R. Doerr et al., Proc. ECOC 2011, Th.13.A.3, Geneva (2011).
 M. Usui et al., Proc. ICEP-IAAC 2015, 660-665, Kyoto (2015)
 T. Pinguet et al., Proc. IEEE GFP 2012, ThC1, San Diego (2012).
 J-M. Fedeli et al., IEEE J. Selected topics in Quantum Electronics 20, p. 8201909 (2014).
 J. Kurumida et al., Proc. ECOC 2014, PDP 1.3, Cannes (2014).
 K. Tanizawa et al., Optics Express 23, 17599 (2015)
 K. Okamoto, Laser & Photonics Review 6, 14 (2011)
 T. Tsuchizawa, ”Guided Light in Silicon-Based Materials,” Handbook of Silicon Photonics (ed. by L. Vivien and L. Pavesi, CRC Press, 2013)
 T. Hiraki et al., Electronics Letters 51, 74 (2015).
 R. Takei et al., Optics Express 23, 18602 (2015).
 H. Nishi et al., Applied Physics Express 3,102203 (2010).
 T. Hiraki et al., IEEE Photonics Journal 5, 4500407 (2013).
 H. Fukuda et al., Optics Express 16, 4872 (2008).
 L. Chen et al., Optics Letters 36, 469 (2011).
 T. Hiraki et al., Proc. OFC 2015, W1A.2, Los Angeles (2015).
 C. Haffner et al., Nature Photonics 9, 525 (2015).
Augmenting traditional transfer moulding with Film Assisted Moulding and Dynamic Insert Technology can deliver a range of benefits to PIC makers. As well as providing necessary packaging attributes, the approaches allow additional functionality to be inserted such as lens structures or through polymer vias. Marco Koelink of the Advanced Packaging Center in The Netherlands provides an overview of the technology, including recent developments in die-attach, and shares device examples from solar, automotive and other key sectors.
Photonic Integrated Circuits (PICs) are developing very rapidly to become one of the most promising technologies for fabrication of functionally advanced, compact and cost-effective optoelectronic devices. Enabling this cost and performance breakthrough is the ability to produce PICs using existing and standard semiconductor processes (Piramidowicz at al ). However, in order to benefit fully from these advantages both the front-end (monolithic integration) and the back-end (packaging) needs to deliver device solutions that meet cost and performance targets.
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Transfer moulding has been the primary process method for microelectronic encapsulation using epoxy moulding compound (EMC). The technology can scale to meet high-volume demands and low-cost requirements. However, traditional transfer moulding has disadvantages such as EMC bleed and resin flash, time consuming mould cleaning, mould wear, package deformation during the ejection process and lead frame deformation or (ceramic) substrate cracking due to clamping.
Dealing with the challenges
Film Assisted Moulding (FAM) offered by the Advanced Packaging Center (APC) deals with these challenges - releasing the compound from the mould and keeping certain surfaces (“windows”) clean from moulding compound. These windows can facilitate emitting or sensing areas of an optical chip. In addition, Dynamic Insert Technology (DIT) has been developed to further optimise the performance of FAM to automatically and dynamically control pressure on one or multiple surfaces while adjusting for height differences and tilt (compensating for most of the tolerances).
Figure 1. Schematic overview of the application of Film Assisted Moulding (FAM) Technology and Dynamic Insert Technology in transfer moulding.
The diagram above shows a schematic representation of the application of FAM and DIT in transfer moulding. A more detailed description of FAM and DIT can be found in Bos et al . These technologies enable the use of many different compound materials (epoxy, silicone) that can be applied in different versions (black, white, clear and combinations thereof). The base materials can also be solid or fluid. In combination with the use of different die-carrier materials such as lead-frames and different substrates (ceramic, metal, FR4, wafer-level) and the option to design exposed open windows in the package, a large variety of packages can be designed to meet the needs of different applications, including optical applications.
Recent developments in PICs, solid-state lighting, communication technology, (medical) sensor technology and other areas require optical packaging solutions that meet both the electrical and optical requirements and allow for high-volume production at reasonable costs. Optical requirements may include total encapsulation (environmental ruggedness), but with defined optical transparency. In other cases, the optical components should be fully exposed to the environment (exposed window). Also, some optical interfacing to the environment might be desirable (connections to optical plastic fibres, lenses for enhanced field of view). Electrical requirements may include a number of IOs, (high) voltage ruggedness, and mechanical requirements may include a defined package layout (for example - QFN, SO, DFN, BGA, LGA or customised), a defined operational temperature range and mechanical ruggedness. Furthermore, designs need to meet different standards, such as automotive or industrial. All of these combinations are well within range of the technology presented.
Compound materials selection
Transfer moulding using FAM/DIT allows for many different compound materials and even combinations of different materials. Epoxy based materials and silicones are most widely used and come in black, white and transparent versions. Traditionally, for microelectronic encapsulation a black compound is used. This consists of an epoxy resin filled with a possible variety of materials (graphite, metal oxides, glass, silicon oxides, etc) that create the colour and a matching coefficient of thermal expansion (CTE) to semiconductor materials. The colour black is preferred because various electronic components are sensitive to light. Similarly, a white compound can be used. In this case, the material consists of a similar epoxy resin containing fillers such as TiO2. These materials can be used to enhance reflectivity of a package or influence the direction of emission patterns of optical sources. An epoxy resin without fillers can be used as a transparent compound. These materials can be used to encapsulate optical components while maintaining optical transparency. However, epoxy resins usually have a large CTE mismatch compared with semiconductor materials, which requires sufficient attention in the design phase to avoid thermo-mechanical stress.
Figure 2. An LED system design using a black epoxy to encapsulate an ASIC (green). Wire bonds and a transparent silicone compound with incorporated lens shape are also shown.
An alternative to epoxy resin is silicone, which has some interesting properties. It is a much softer material than epoxy resin, leading to much less thermo-mechanical stress. It is much less susceptible to optical (UV) degradation, making it ideal for applications with long life-time requirements and high radiation levels (for example - concentrated photovoltaics, as shown below). However, because the material is soft, it can be hard to saw, which can be difficult for high-volume production. Silicone compound is a fluid based material which makes it difficult to use and absolutely requires double-film based moulding (FAM).
Figure 3. Examples of a solar collector (concentrated photovoltaic) in a white compound.
Substrate selection and package layouts
Transfer moulding is a flexible technology, which allows for many different substrates to be used. The traditional lead-frame technology has many advantages - it is a well-known technology, has good adhesion properties to compound materials, it is cost-effective in mass production and allows many different technologies for die-attach (gluing, soldering, welding, sintering etc). Alternatively, different substrate materials can be used: metal, ceramic, flex-foils, FR4 or wafer-level. FR4 materials (or similar) can be tricky: at elevated temperatures they can outgas leading to decreasing adhesion. The use of double-film based moulding (FAM) enables large areas of substrates to be free of compound, which can be advantageous for secondary level packaging or thermal considerations.
Figure 4. Left: a lead-frame based design for an automotive optical transceiver. The devices are fully encapsulated in clear compound with integrated alignment bumps to facilitate the in-coupling of light into a plastic optical fibre. Middle: a lead-frame based design for a photometric sensor, fully encapsulated in clear compound. Right: a fully integrated (analog and digital) optical sensor system in a similar lead-frame bases design fully encapsulated in clear compound with a small optical lens in the right bottom corner (see also figure 6, left) .
Wafer-level moulding has attracted significant interest over the last couple of years. Combined with, for example - the affordable use of Through Wafer Via technology in the front-end semiconductor design, wafer-level moulding allows for very cost-efficient package designs. All compound and substrate materials can be combined in a range of standard or customised package layouts. This includes package layouts such as DIP, QFP, QFN, DFN, SOP, BGA, PGA and more. Leaded packages such as DIP and SOP are often used in automotive applications because of their proven reliability. However, based on their cost efficiency, leadless packages such as QFN are increasingly used not only in automotive, but also in avionics and other demanding industrial areas. In addition to these standard packages, both customised versions of these standards package layouts as well as fully customised packages are easily feasible.
Figure 5. An example of a device on a wafer-level substrate. After moulding (using a combination of compounds) the individual devices can be sawn from the wafer.
Advances in die-attach and bonding technology
Numerous die-attach technologies are available that can be combined with transfer moulding, including epoxy, eutectic and soft-solder. However, recently two new technologies have become available that are of particular interest in demanding thermal applications (high power or high power-density): Silver (Ag) sintering and ultrasonic soldering. Ag-sintering is a new die-attach and bonding technology offering a void-free, strong bond, superior thermal (> 200 W/mK) and electrical conductivity resulting in high yield and increasing the output of your device and lifetime at the same time. The sinter process takes place at 200-250 ˚C, but the resulting bond does not melt until 962 ˚C (melting point of silver). This allows for many subsequent reflow processes. Research in Ag-sinter materials has been ongoing for several decades and over the last 2-3 years the technology has been industrialised. It is rapidly being adapted by suppliers of automotive power electronics (for electrical cars), but also has great potential for high power (semiconductor) lasers, automotive LED head-lighting, LED street lighting and more. Ag-sintering requires all surfaces to be metallised with preferbly either silver or gold. This limits the application area somewhat.
Recent developments in ultrasonic soldering, especially in the formulation of new advanced solder materials, have created very intersting opportunties to solder many different materials (metals, ceramics, glasses) over a large temperature range (140 ˚C up to 450 ˚C) without the use of any flux or additional metallisation. See Rass [3, 4]. Specifically, the technology is interesting for bonding different unmetallised surfaces for which now mainly (epoxy) glues are available. These new ultrasonic soldering materials have a thermal conductivity (50-100 W/mK) that outperforms these epoxys. They are already being used in power-electronics cooling and are now being tested for applicatons in optical (semiconductor) packaging. Initial results look very promising.
Supplying additional functionality: lenses, filters and channels
Typically, packaging is used to protect the internal device from external influences, such as impact and corrosion, holds the leads or connections in place and transfers the heat from the interior to the environment. However, transfer moulding using FAM and DIT provides the opportunity to create additional functionality. In clear compounds, lens shapes can be created to enlarge the field of view of detectors or to create structures (“alignment bumps”) that facilitate the in-coupling of light into optical fibres. The absorption spectra of different (transparent) compound materials vary, enabling the design of “optical filters” for over-moulded devices. Mixing a defined concentration of TiO2 particles into a clear compound also creates the opportunity to design diffusive filters for over-moulded devices. Finally, channels can be created in the package (micro-fluidic) that can be used in combination with optical devices.
Figure 6. The application of different design studies to create lens structures in packages. The smallest diameter that can be achieved is well below 1 mm.
Through polymer vias (TPVs)
Working with Delft University of Technology, APC has co-developed a method for the fabrication of vertical interconnections (vias) to connect chips, devices, interconnection layers and wafers in out of plane directions. The advantages of vertical interconnects for 3D-integration are: shorter total length of the interconnections and the ability to interconnect stacked devices combined with a dense high-aspect-ratio. Our approach relies on patterning micro-pillars in a 350 μm thick layer of photo resist on a carrier wafer or substrate. The pillars are conformal coated with a metal film and subsequently encapsulated inside an epoxy moulding compound, resulting in vertical through-polymer interconnect vias (TPV). For subsequent interconnect processing, a clean and free of epoxy top surface of the pillars is crucial, which was achieved by using foil assisted transfer moulding technology.
Figure 7. Left: a test sample showing several electrical Trough Polymer Vias (TPVs), enabling high density vertical optical and/or electrical connections in a package. Right: (a) a schematic view of the TPV’s that need to be encapsulted, (b) transfer molding of epoxy mold compound entering the cavity sideways, perpedicular to the TPV’s, and (c) the completely molded TPV structure.
The technology has been proven for electrical interconnections (see Kengen et al ), but can -- in principle -- be extended to optical interconnections as well by choosing a suitable optical compatible photo resist material, coating the pillars with a reflective metal film and leaving the top side of the pillars exposed from either metal or compound material.
Unfortunately transfer moulding cannot address all possible requirements for PICs. The hermeticity that can be achieved using moulding compounds is limited to approximately Moisture Sensitivity Level three (MSL 3). Stricter requirements for hermetic packages require other materials such as metal packages. Some medical (optical) applications that expose packages to in vivo situations require biocompatibility that can also not always be met with existing compounds. However, the largest drawback is the current inability to encapsulate pig-tailed devices (using SM or MM glass fibres) on an industrial scale, mainly because of the required mechanical precision. Although it might, in theory, be possible to industrialise the process of pig-tailing followed by encapsulation by transfer moulding, it is very hard to overcome the necessary investments and justify the business case. This is unfortunate since fibre connected devices represent a large portion of all PICs. There is interesting progress being made in designing (mechanically) tolerant coupling structures (e.g. Soganci et al ), but at present these results are insufficient to enable viable industrial transfer moulding design solutions.
Transfer moulding has been the primary process method for microelectronic encapsulation and allows for high-volume and low-cost industrialisation solutions. Building on this, transfer moulding technology from Advanced Packaging Center BV has been augmented with Film Assisted Moulding (FAM) and Dynamic Insert Technology (DIT), which further expands the range of design solutions. An important feature of FAM is the ability to keep certain surfaces (“windows”) clean from moulding compound. These windows can facilitate emitting or sensing areas of an optical chip. Several design solutions are discussed and examples are given, including the use of different and combinations of moulding compounds (black, white, transparent in both epoxies and silicones) and different substrates (lead frames, substrates such as metals, ceramics, FR4 and wafer-level). These materials can be combined in standard packages (industry standards), variations thereof and complete customised packages. Features such as lens-shapes can be included in the package design which gives the package additional functionality such as enlarging the field-of-view of e.g. detectors or enabling the in-coupling of light into an optical (plastic) fibre. Two new developments in die-attach technologies are introduced, offering interesting opportunities for high-power or high-power-density applications: Silver (Ag)-sintering and ultrasonic soldering. Some limitations of the transfer moulding technology are discussed, most specifically the current inability to encapsulate pig-tailed devices (using SM or MM glass fibres) on industrial scale.
References and further reading
 Piramidowicz, R., Stopinski, S. T., Lawniczuk, K., Welikow, K., Szczepanski, P., Leijtens, X. J. M., & Smit, M. K., (2012). Photonic integrated circuits: a new approach to laser technology. Bulletin of the Polish Academy of Sciences: Technical Sciences, 60(4), 683-689. DOI: 10.2478/v10175-012-0079-5
 Bos., A., Wang, L., Van Weelden, T., “Encapsulation of the Next Generation advanced Mems & Sensor Microsystems”, Microelectronics and Packaging Conference, Rimini, Italy, June 15-18, 2009. EMPC 2009
 Rass, I.J., “Ultrasonic Soldering of Metals, Light, Metals, Glasses and Ceramics”, Löt Conference, Aachen, Germany, June 7-9, 2016.
 Hillen, F., Pickart-Castillo, D., Rass, I.J. and Lugscheider, E., “Solder Alloys and Soldering Processes for Flux-Free Soldering of Difficult-to-wet materials”, Welding & Cutting, vol. 52, no. 8, pp. E162–E165, 2000.
 Kengen, M., Poelma R.H., Van Zeijl, H.M., Van Weelden, A., Boschman, E. “Through-Polymer-Via for 3D Heterogeneous Integration and Packaging”, Minipad 2015, April 22-23, Grenoble France.
 Soganci, I.M., La Porta, A., and Offrein, B.J., "Flip-chip optical couplers with scalable I/O count for silicon photonics," Optics Express, vol. 21, no. 13, 16075-16085, 2013
Marco Koelink is business development manager at the Advanced Packaging Center based in Duiven, The Netherlands. He holds a PhD/MSc in Applied Physics from the University of Twente and an MBA from Tilburg University. His background includes experience with a.o. Philips and NXP in the semiconductor industry, display technology, solid state lighting, medical- and industrial equipment. Marco’s previous roles include Development Manager for NXP RF Power, Director of materials analysis for Philips Research and Market Intelligence manager for Philips Lighting.
Web - www.apcenter.nl
Email - MarcoKoelink@APCenter.nl
It’s time to highlight the tremendous progress in the development and application of photonic integrated circuits (PICs). James Tyrrell, features editor of PIC International magazine and a member of the PIC International conference team, announces a new industry awards programme recognising advances in photonic integration.
It’s been a busy year for the PIC International team. In March, PIC International 2016 brought together experts in photonic integration from all over the world for a packed two-day technical conference in Brussels. And then in June, we launched issue #1 of PIC International magazine to keep the conversation going all year round and provide feature-length coverage of progress in device development and application.
Speaking with equipment providers, software developers, chip makers, packaging experts, test and measurement specialists, and end-users of the technology - interest in photonic integrated circuits is arguably at an all-time high. Devices have come a long way thanks to the skills and expertise of leading lights in the sector. And to recognise the advances in photonic integration powering today’s technology we are proud to unveil the PIC Awards 2017.
Brought to you by the team behind PIC International Conference and PIC International magazine -- and voted for by the PIC industry -- the awards span six categories:
Nominations for the PIC Awards are now open, and online voting will commence in January 2017. We are encouraging all stakeholders within the PIC community to get involved and make this the must-enter awards for the industry. It’s a great opportunity to recognise advances in photonic integration and celebrate the success stories so far.
The awards ceremony will take place at PIC International Conference on 7th March 2017. And we hope you’ll be able to join us. To book your place, visit - www.picinternational.net
Dates for your diary
Nominations open - 1st November 2016
Nominations close - 9th January 2017
Shortlist announced - 16 January 2017
Voting opens - 16 January 2017
Voting closes - 21 February 2017
Winners announced - 21 February 2017
Awards ceremony - 7 March 2017
About the author
James Tyrrell is a freelance science and technology writer working with Angel Business Communications on PIC International magazine and its sister conference PIC International.
Developers are working hard to simplify the assembly of integrated photonic devices so that chips can enter a broad range of markets at more attractive price-points. Ian Oxtoby, optical packaging manager at Optocap, shares the firm's strategy for bringing down the cost and complexity of PIC packaging.
Historical PIC development
Since Optocap’s formation we have been involved with fibre coupled optical products, supporting multinational companies, SME’s & university research groups with their developments and looking at new applications for the technology. We have seen significant changes in the requirements since 2003.
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While research organisations and collaborative programs have focused on evolving the technology, the success of PICs in the market rests on heavily on price. Historically, it has been challenging to justify the cost of the customised packages, fibres and alignment processes - even at the prototyping stage.
The expectation is that the implementation cost of new products should be relatively low, because the final product costs of optoelectonic devices in high volume is relatively low. However, the development of highly tuned products in high volume quantities often stems from a significant design cycle that has been optimised over many years. With PIC technology we need to borrow not only from the optoelectronic industry, but also build on experiences from the microelectronics sector in order to match our customer’s ambitions.
Optocap understands that new technologies looking to compete with more mature products need to significantly reduce footprint size, power usage or price-point.
The landscape of existing PIC requirements and packaging solutions is not only vast, but hugely variegated in its needs. This has often led to inflexible, application-oriented expensive and tailored solutions in most cases. We at Optocap intend to bring down the complexity and cost of PIC packaging through the introduction of fotonIC - a flexible, robust solution which can cater to the broader needs of industry, while retaining the ability to tailor the platform to more specific applications.
Figure 1. Adaptable approach: 'fotonIC' platform with flexible design adjustments.
Managing expectations & standardisation
In industry, generally it is expected that once the customer has designed a PIC for their application, then it can be packaged to the outlined criterion. This approach often results in reinventing assembly processes already developed as slight variations can have significant implications.
Where customer design sensitivities are more forgiving, a standardised platform needs to address the needs without modification. With a set of design rules, it’s important we ensure correlation with our customers and that their designs are focused on meeting key criteria to avoid the more costly issues.
The entry fee for customised packaging is higher and redesigning of the package is costly once a PIC has been designed. However, by using the standard platform, customers can test chips and modify them before committing to this path.
Ensuring that the chip is designed to match the prototyping platform can, not only be cheaper, but critically it can also enable faster package processing. With development time limited and time-to-market so critical, standardisation can only help the diverse PIC package industry.
A standardised approach to package design for pitch, affects the package design cost significantly too. The reason is the utilisation of standard off-the-shelf parts as well as in-house already developed processes. The package cost mainly comes from, for example, developing new optical alignment processes and designing new assembly procedures. Cost increases further with the addition of supporting optical/mechanical components designed specifically for that package only.
By allowing a standardised package assembly to guide a PIC design, the redesigning of package and optical alignment procedures is no longer necessary. This allows for standard FVA Fibre alignment procedures, however, with potentially a compromise on coupling efficiency.
Figure 2. Attributes of standard, customised and custom packages.
Another option that we have chosen to minimise costs is the use of our precision epoxy die attach processes. Often PICs are difficult to metalise and expensive as well. We propose not to use solder die attach unless extreme thermal performance is required. With performance thermoelectric coolers, customers can avoid metallisation on parts along with complexity of metalising the PIC. Optocap’s proprietary low stress epoxy die attach processing is a further option.
Figure 3. Technical details
By standardising a packaging platform, we significantly reduce the assembly and design time for the customer. By eliminating the need to redesign the layout, it’s possible to make the standardised assembled and functioning package available to the customer in less than third of the normal time.
It can be appreciated that a single platform cannot possibly suit all situations and applications. However, Optocap’s ‘fotonIC’ platform is targeted to standardise most prototyping requirements. And the flexibility provided by fotonIC platform can contribute towards its acceptance as general standard platform for PIC alignment.
Figure 4. Technical layout for standard/customised PIC alignment.
The fotonIC platform is able to adapt the electrical I/O to customer requirements. If RF connections are required, they can be incorporated in the connection design on PCB. The layout is flexible and can easily be adapted for 3sides electrical contacts.
Another flexibility this platform provides is in adapting to an optical alignment process. In addition to its standard butt-coupled arrangement, several other optical alignment schemes can be adapted - for instance, grating couplers, lensed fibres, angled waveguides etc. These additions can be customised to cater for more specific individual customer needs and can be discussed prior to any assembly assignment.
Figure 5. Summary of the fotonIC Platform
Ian Oxtoby is optical engineering manager at Optocap. He is responsible for the design, verification and qualification of optoelectronic packaged products within the company. With over 20 years in the optical and microelectronic packaging industry, Ian has worked in package development and manufacturing in multiple industries, including telecoms, medical, defence, printing, automotive and aerospace.
To keep pace with an increase in the demand for high-performance optical components, producers will need to consider automation of their processes in more detail. Dylan J. Burke of Yelo – a firm specialising in automated device measurement – looks at what’s driving the market and discusses the challenges that device makers face in relation to burn-in and test of devices at high volume. Included in his review are examples of the developments Yelo has been working on to help PIC firms in ramping up production.
The current market scenario
Our digitalised world demands faster network speeds and greater bandwidth. Go to any photonics- or optoelectronics-related industry trade show or conference in the world and it’s one of the hot topics on everyone’s lips and minds. There is a genuine buzz in the industry – 100 Gbps networks are exciting and everyone wants a piece of that market.
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We are living in a time where more people are using social media sites and apps to share their videos, pictures, live streams and even virtual reality experiences. There are other developments to consider too, such as big data and cloud computing, the internet of things, and digital healthcare.
Photonic integrated circuits (PICs) are the bedrock of making this happen and to put it into perspective, the use of optical components in the large-scale data centre market is forecast to grow by approximately 700% over the next eight years and the value of this market is estimated to be worth over $400 million by 2024. These are some truly astronomical figures and this demand is going to expand the need for optical components with a speed of 100 Gbps, low power consumption, small die size of 0.25m2 with 20 micron tolerance and 100 micron electrical pad sizes.
The importance of burn-in and test data
To succeed, PICs need to be not just fast, but reliably fast. For light sources, this means applying a burn-in process - in other words, running components under a continuous period of operation to check for defects and ensure that every device shipped is up to standard. The aim of production burn-in is to stress the laser diode crystal structure using higher than normal operating current and operating temperature. Under these conditions a point of so-called infant mortality will be detected. Typical soak temperature ranges from 85°C to 150°C and typical current ranges are 50-150% of the normal operating current.
Having this reliability data is essential to device makers in winning repeat orders and can justify a premium on price. The data also goes hand in hand in appraising new layouts and optimising manufacturing.
The challenges of scaling up
One of the real challenges for companies involved in the industry is how to scale-up their output. What are the options for speeding up the production process, which includes the assembly, packaging and testing of optical devices?
The obvious answer is full automation. As the demand for optical devices increases, the firms that will successfully capture market share will be the ones who can scale-up their production lines using automation to increase the throughput of devices getting into the field. What’s more, automation can free-up a firm’s engineering resource to be used more efficiently in other areas.
Yelo has been developing a range of test equipment and services to help device makers in scaling-up their processes. Our burn-in systems (see below) along with our support and maintenance services are widely used in the telecommunications and data communications industries and help device makers get the test data they need to produce a qualification report for the requirements outlined in the Telcordia GR-468 document.
Figure 1. Yelo Y1000L burn-in and life test system.
Yelo wants to ensure that device makers are aware of the importance of having reliability test data. To give an example - we recently worked with a leading US based scientific instrumentation organisation that didn’t have any data, but needed their devices to have a 10 year lifetime. It actually turned out that their devices had a 50% failure rate after just 6 months and were late in getting their product to market. To help them, we were able to propose a detailed life test strategy which included;
We also had a discussion with an academic institution on best practice for experiments and test procedures. Yelo are currently testing their devices in-house and are sending the client reliable test data every two weeks and they now have a competitive product to take to market with a reduction in warranty costs and field visits.
Our most recent development is the LIV (light – current – voltage) test instrument (figure 2) and works as an integral part of the testing process. Our typical process is to perform a pre burn-in LIV measurement on devices, burn-in devices at the conditions required by the client and then perform another post LIV measurement to monitor any change in threshold.
Figure 2: Yelo LIV test instrument with test fixture
Other hurdles to overcome
Challenges remain for burn-in and test – for example, as devices move to smaller sizes, the handling of components will need to adapt accordingly. At Yelo, we are actively researching and developing solutions to these problems.
Dylan J. Burke is marketing coordinator at Yelo.
Web - www.yelo.co.uk
Email - email@example.com
Ton Backx, CEO of PhotonDelta, has a new goal in the coming year. He plans to kick-start international discussions about the optical technologies needed for global society two decades from now. He outlined what’s happening and why to Jonathan Marks.
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Figure 1. Ton Backx
Photonics is already key to solving the challenges of a modern world. It enhances our quality of life; safeguards our health, safety and security. It is also key to solving the exponential demand for energy coming from the growing number of datacentres. Many technologies are currently exhibiting exponential growth, although it isn’t new.
It began 50 years ago, as the age of micro-electronics dawned and powered a wide range of applications. Telecom has proved to be the initiator for exponential growth in integrated photonics applications. We’re also seeing similar trends in biosciences and advanced sensors. But without a roadmap, there’s a danger that we lose sight of the real-world bottlenecks and challenges ahead.
“We think there’s a need for structural discussion on a global basis about a horizon that’s 20 years away” says Ton. “If we simply refine current technologies, there is no guarantee that we will meet societal technology demands by 2025, let alone 2035.”
So, the sooner we understand more detail about the path ahead, the better.
“Take the tremendous growth in Internet and Telecom traffic. Global bandwidth requirements have exceeded most expectations. Internet bandwidth is expanding with a factor of between 1.5 -1.8 times a year. But whichever figure you believe, if you look at the total traffic that the world needs to handle, within 10 years it means is 600-fold increase in the bandwidth needed to cope with it all. Or things come to a grinding halt.”
Technology Breakthroughs in Eindhoven
“But there is hope coming from ongoing research. In our labs at the Institute for Photonic Integration in Eindhoven, for instance, we've built a working demonstrator which can communicate at a speed of 255 Terabits per second. By comparison, in today’s commercial long-haul optical fibre connections, the maximum speeds applied are around 0.16 Terabit per second.
Since we estimate that bandwidth needs within a decade will be around 600 times greater than today, then we know that we have a good chance to develop this technology in time to meet market demand. And we can also make more accurate projections on the energy required to power the datacentres when they are called upon to handle that kind of traffic.
We often forget that it can take anything between 10-15 years to go from an idea in a lab into a technology that a manufacturer can build in medium - or large quantities. And we know we cannot do this in isolation.
Importance of the long-term view
As a global society, we need to look ahead 15-20 years. We need to carefully examine the projections to work out which technologies we will require. Is there a gap between what is expected by industry and what research organisations believe is feasible to deliver within that timeframe?
Perhaps the biggest proponent of the long-term view is Amazon CEO Jeff Bezos. “If everything you do needs to work on a three-year time horizon, then you’re competing against a lot of people,” Bezos told Wired in 2011. “But if you’re willing to invest on a seven-year time horizon, you’re now competing against a fraction of those people, because very few companies are willing to do that.”
Ton Backx continues. “It’s true, several optical science research teams on both sides of the Atlantic have been developing roadmaps looking 5-10 years out. They are doing important work. But, in our opinion, they don't go far enough or have a broad enough scope to ensure you detect major technical challenges and roadblocks early enough. We are currently setting up a procedure to change that.”
Two types of workshops
Figure 2. Active workshop session
“I am currently drawing up a plan of how these roadmaps would be built. We're aiming to make them into living documents, revised on an annual basis. In that way, they can keep track of the real-world trends and adjust accordingly. We also need to ensure that the procedures to do this will stand for several decades.”
“We're planning to do this with two types of active workshops to be hosted in The Netherlands next year.
“In March 2017, we will have a preparatory meeting for the first main workshops. We’re inviting 10-12 of the world top experts who cover research and development in key technologies. These specialists understand where we are in applied technologies and hurdles that still need to be solved before manufacturers in the private sector can take over. This preparatory team is tasked with the preparation of the first global long-term roadmap development conference.”
“We expect the main workshop to be held in the Netherlands in June 2017 involving around 150. These people will come both from research as well as industry. The first workshop will be invitation-only to ensure we can refine the topics that require attention in the roadmap. But once established, the subsequent workshops in 2018 and beyond will be open to anyone who can actively contribute and is willing to participate.”
“We need to better understand what the market expects and the specific technology needs. What can be done to lower the cost of the technology to the tipping point where there is widespread adoption? How complex are the challenges to be solved two decades from now?”
Photonics Chips are a good example
“In other sectors like healthcare we're seeing ambitious roadmap programs being launched. The US National Cancer Moonshot, for instance, has set a goal of doubling the rate of progress – to make a decades’ worth of advances in five years.”
“We will probably cast the horizon even longer - 15-20 years ahead. And certain big challenges require several steps in between the 5-year forecast and the 20-year projection.”
“Another example is the photonics integrated chip. Currently, chip-design companies can put up to 2000 components integrated onto a single chip. By 2025, and applying the exponential growth factor, we would expect 100,000 devices on a chip of similar size.”
“But as you shrink the size and increase the integration density of components, there comes a point where you start to see interactions between them which may have consequences for the performance. Components may need to be isolated, and at the moment we don't have a way to do this. There are thoughts on materials, but nothing firm. We need several years to solve these issues to reach our goal.”
Understanding complex paths
“Roadmaps also help to judge the complexity of the problem. It may be that research and development projects can be coordinated to run in parallel, or an application put on hold until a supporting technology has reached a given milestone. In the end, it gives a clearer picture of the priorities and where investment can best be channelled for maximum effect.
We're also extending the invitation to other sectors which include nanotechnology groups working on advanced photonic sensors in life sciences, agriculture and forestry, as well as autonomous vehicles and big data science. I am currently preparing an initial discussion document and welcome thoughts from the community. The structure is going to be important because we hope it sets a framework for discussions that can continue for a long time. I see it as complementary to the important debates taking place in Brussels at PIC International.
I've also been pleased by responses from industry specialists who see the need for roadmaps. From their perspective, the hardest challenge is to identify which intellectual property is worth investing in, what IP are others expected to develop and how do they match.”
Outreach to other hotspots has begun
Figure 3: Bert Pauli
PhotonDelta has received full backing from regional government in this endeavour. Bert Pauli is vice governor Economics and International affairs for the province of Noord-Brabant. He has a heritage of working in industry and always understood the need for international outreach.
“The South-Eastern part of the Netherlands has always been a world-class high-tech hub, conducting pioneering research into optical devices and integrated circuits. It’s where Philips invented the Compact Disc and the DVD. Related enterprises have also sprung up – the region is home to ASML, the world’s largest supplier of machines to manufacture chips as well as Holland’s leading business park, High Tech Campus Eindhoven.”
“The secret to ASML’s success lies in their ability to work with 2400 small and medium enterprises. All these companies share a common goal - to produce the best quality goods and services in new, agile and clever ways. In this region, we have pioneered methods to ensure open, trusted and transparent collaboration. And now that’s paying off. We've succeeded in accelerating innovation in sectors such as aerospace, pharmaceuticals, and logistics - all sectors which have traditionally been very closed. On December 1st 2016 we opened the Jheronimus Academy of Data Science. Developments in Big Data analysis are going to need quantum computing speeds and security. And photonics has many relevant technologies to achieve this.”
Government as a public entrepreneur
The role of Brabant regional government is increasingly a form of “managed serendipity”.
“We see a growing need to be far more forward thinking, anticipating what's coming - not what's already been discovered, “continues Pauli.
“We maintain a “helicopter view” because individual sectors often get locked into their own circles. We see connections emerging between photonics, robotics, healthcare and data science. By keeping an active dialogue going with large and small companies as well as the many research institutes we have close-by, we're able to trigger opportunities that they cannot see themselves.”
“Earlier this year, we supported the launch of PhotonDelta, which we see as an important international initiative connecting the research communities with high-tech enterprise and investors. A vibrant ecosystem has quickly established itself because all the elements needed for innovation are very close by. In helping to form PhotonDelta, we quickly recognised the need for alliances beyond our region. In the Dutch province of Twente for example, the MESA+ Nanolab, LioniX International, PhoeniX Software and the University of Twente have each developed important photonics technologies which complement the work being done in North Brabant.”
“We're also grateful for the outreach assistance we’re getting from the innovation attachés at the Netherlands embassies abroad. They are important in our efforts to explain the need for these long-term technology roadmaps.”
Realising our preferred future
“There no doubt in our minds. We’ve entered a new era for photonics. Public investment is still needed to bridge the gap between working prototypes leaving the research lab and the point at which the chips are ready to be manufactured in quantity. It’s at that point where the private enterprise takes over.”
“We’re an active participant in the Vanguard Initiative. It has grown into an excellent example of 30 of Europe’s smartest regions collaborating on the grand challenges facing our planet. And what we’ve learned by working closely with companies and institutions in Baden-Württemberg, Germany, Flanders, Belgium, and Emilia Romagna, Italy, is now being applied elsewhere.”
“With Photonics, we're currently reaching out to the leading technology hubs in the world. We have already received interest from organisations like the American Institute for Manufacturing Integrated Photonics and the International Consortium for Advanced Manufacturing Research (ICAMR) based in Central Florida. And in the last few weeks, companies in several parts of Europe as well as China, Singapore, Taiwan and Israel have shown interest in actively supporting us.”
“Photonics has already been chosen by the European Commission as one of the 6 key enabling technologies - now we're ensuring that the workshops we set up next summer will be open to anyone who can actively contribute and participate. Knowing what's going on and what needs to be done for the future is in everyone’s interests.”
To find out more about in participating in next year’s road-mapping workshops, contact Ton Backx via the following email address - firstname.lastname@example.org.
Images in this article were provided by Photondelta.
Images in this article were provided by Photondelta.
How can you improve the coupling efficiency between optical fibres and photonic integrated circuits? Florent Gardillou -- technical project leader and business development manager at Teem Photonics -- takes a detailed look at the latest transposer technology and its application in silicon photonics-based designs, as well as reviewing the firm’s broader activity in advancing PICs.
In the past years, silicon photonics (SiP) has captured the attention of the photonics integrated circuit (PIC) community by offering a compact and highly scalable solution across a range of applications. But there are technical issues to contend with. The main downside of SiP waveguides’ high-confinement feature is the poor coupling efficiency when interfacing with optical fibres. Indeed, the typical cross section of a silicon waveguide (0.5 x 0.3µm) is more than 300 times smaller than the core of standard optical fibres (8µm diameter).
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The « top coupling » solution has raised great hope over the last decade. The principle is to illuminate, from the top surface, a grating coupler integrated on the silicon chip through a nearly vertical fibre. But, despite the huge effort made by many groups over the world on this topic, this solution does not appear to lead to a consensus, at least for future high-performance components.
The main reasons are :
As a result, « edge coupling » configurations are back in contention, helped by the integration of « edge couplers » on SiP chips. The spot size converters (SSC) and the inverted tapers allow an adiabatic transition from a sub-micronic mode field diameter (MFD) to larger ones, available with lensed optical fibres (MFD 2.5-4µm @ 1550nm).
But lensed fibres present several drawbacks for SiP chip coupling. First of all, ensuring a stable coupling efficiency packaging with lensed fibres still remains challenging. Moreover, the realisation of lensed fibres array for the coupling of the future multi-channels components is compromised by:
WAFT : the glass optical transposer for SiP connection
Based on its ioNext platform for the manufacturing of photonic integrated circuits on glass, Teem Photonics has recently developed a new optical transposer component for edge coupling to tackle these issues.
Figure 1. Principle of the WAFT component which combines a fibre spacing concentrator (FSC) and an array of mode converter waveguides
As illustrated above, the WAFT (waveguides array to fibre transposer) is combining an array of mode converter waveguides with a fibre spacing concentrator (FSC). The mode converters that are integrated on the WAFT component enable a good correspondence to the tapered waveguide MFD of the SiPhotonics chips. Indeed, they provide a smooth transition from the MFD of a standard fibre to a much tighter one. Then, the FSC provides an optical pitch reduction down to 10µm which shrinks the area dedicated to the optical coupling on the SiP chip and therefore also induces a real cost saving.
The implementation of the ioNext platform for the manufacturing of the WAFT components provides many key features for the fibre-to-silicon-chip connection:
The footprint of the glass component can be reduced even more by shaping the exit of the chip as shown below (Figure 2-c). Moreover, the direct attachment between the WAFT chip and the SiP chip provides more stable and robust packaging.
Figure 2. examples of WAFT products: (a) 10-channel WAFT attached with a PM fibres array unit, (b) 64-channel WAFT attached with a SMF fibres array unit and a SiP chip. The WAFT chips can be shaped in many ways to reduce the footprint on the SiP chip side (c).
The main features of the WAFT components are detailed below.
Table 1. A list of WAFT component features. The parameters indicated with * are to be considered without the additional connectors loss.